LMS12 Datasheet, PDF (1/9 Pages) LOGIC Devices Incorporated – 12-bit Cascadable Multiplier-Summer

DEVICES INCORPORATED
DEVICES INCORPORATED
LMS12
LMS12 ^{12-bit Cascadable Multiplier-Summer}
12-bit Cascadable Multiplier-Summer
FEATURES
DESCRIPTION
u 12 x 12-bit Multiplier with
Pipelined 26-bit Output Summer
u Summer has 26-bit Input Port Fully
Independent from Multiplier
Inputs
u Cascadable to Form Video Rate FIR
Filter with 3-bit Headroom
u A, B, and C Input Registers Sepa-
rately Enabled for Maximum
Flexibility
u 28 MHz Data Rate for FIR Filtering
Applications
u High Speed, Low Power CMOS
Technology
u 84-pin PLCC, J-Lead
The LMS12 is a high-speed 12 x 12-bit
combinatorial multiplier integrated
with a 26-bit adder in a single 84-pin
package. It is an ideal building block
for the implementation of very high-
speed FIR filters for video, RADAR,
and other similar applications. The
LMS12 implements the general form
(A•B) + C. As a result, it is also useful
in implementing polynomial approxi-
mations to transcendental functions.
ARCHITECTURE
A block diagram of the LMS12 is
shown below. Its major features are
discussed individually in the follow-
ing paragraphs.
MULTIPLIER
The A11-0 and B11-0 inputs to the
LMS12 are captured at the rising edge
of the clock in the 12-bit A and B input
registers, respectively. These registers
are independently enabled by the
LMS12 BLOCK DIAGRAM
ENA
A 11-0
12
A REGISTER
B 11-0
12
B REGISTER
ENB
CLK
24
PRODUCT REGISTER
SIGN
EXTENDED ₂
24
FTS
C25-0
26
26
S25-0
26
26
OE
ENA and ENB inputs. The registered
input data are then applied to a
12 x 12-bit multiplier array, which
produces a 24-bit result. Both the
inputs and outputs of the multiplier
are in two’s complement format. The
multiplication result forms the input
to the 24-bit product register.
SUMMER
The C25-0 inputs to the LMS12 form a
26-bit two’s complement number
which is captured in the C register at
the rising edge of the clock. The C
register is enabled by assertion of the
ENC input. The summer is a 26-bit
adder which operates on the C
register data and the sign extended
contents of the product register to
produce a 26-bit sum. This sum is
applied to the 26-bit S register.
OUTPUT
The FTS input is the feedthrough
control for the S register. When FTS is
asserted, the summer result is applied
directly to the S output port. When
FTS is deasserted, data from the S
register is output on the S port,
effecting a one-cycle delay of the
summer result. The S output port can
be forced to a high-impedance state by
driving the OE control line high. FTS
would be asserted for conventional
FIR filter applications, however the
insertion of zero-coefficient filter taps
may be accomplished by negating
FTS. Negating FTS also allows
application of the same filter transfer
function to two interleaved datas-
treams with successive input and
output sample points occurring on
alternate clock cycles.
ENC
Multiplier-Summers
1
08/16/2000–LDS.S12-J