LF2247 Datasheet, PDF (1/10 Pages) LOGIC Devices Incorporated – Image Filter with Coefficient RAM

DEVICES INCORPORATED
DEVICES INCORPORATED
LF2247
LF2247 ^{Image Filter with Coefficient RAM}
Image Filter with Coefficient RAM
FEATURES
DESCRIPTION
u 66 MHz Data Input and Compu- The LF2247 consists of an array of four ^{an asynchronous three-state output}
tation Rate
11 x 10-bit registered multipliers
enable control to simplify the design
1
u Four 11 x 10-bit Multipliers with
followed by a summer and a 25-bit
of complex systems. The pipeline
Individual Data and Coefficient
Inputs and a 25-bit Accumulator
accumulator. The LF2247 provides a latency for all inputs is five clock
coefficient register file containing four cycles.
2
u Four 32 x 11-bit Serially Loadable
Coefficient Registers
u Fractional or Integer Two’s
Complement Operands
u Package Styles Available:
• 84-pin PLCC, J-Lead
• 100-pin PQFP
32 x 11-bit registers which are capable
of storing 32 different sets of filter
coefficients for the multiplier array.
All multiplier data inputs are user
accessible and can be updated every
clock cycle with either fractional or
integer two’s complement data. The
pipelined architecture has fully
registered input and output ports and
A 25-bit accumulator path allows
cumulative word growth which may
be internally rounded to 16 bits.
Output data is updated every clock
cycle and may be held under user
control. The data inputs/outputs and
control inputs are registered on the
rising edge of CLK. The Serial Data In
signal, SDIN, is registered on the
3
4
5
LF2247 BLOCK DIAGRAM
ENBA
6
5
A4-0
COEFFICIENT REGISTER FILE
SDIN
Coefficient
Coefficient
Coefficient
7
Coefficient
SEN
Register 1
SEN
Register 2
SEN
Register 3
SEN
Register 4
SCLK
(32 x 11-bit)
SCLK
(32 x 11-bit)
SCLK
(32 x 11-bit)
SCLK
(32 x 11-bit)
D19-0 ENB1
D29-0 ENB2
D39-0 ENB3
D49-0 ENB4
8
10
11
10
11
10
11
10
11
9
10
22
ACC
FSEL
25
MS LS
22
OCEN
11
OEN
CLK
TO ALL REGISTERS
(EXCEPT COEFFICIENT REGISTERS)
16
S15-0
1
Video Imaging Products
08/16/2000–LDS.2247-H