L8C201 Datasheet, PDF (1/22 Pages) LOGIC Devices Incorporated – 512/1K/2K/4K x 9-bit Asynchronous FIFO

DEVICES INCORPORATED
DEVICES INCORPORATED
L8C201/202/203/204
512/1K_L/2₈K_C/4K₂x₀9₁-b_/i₂t A₀s₂yn_/c₂h₀ro₃no_/u₂s₀F₄IFO
512/1K/2K/4K x 9-bit Asynchronous FIFO
FEATURES
DESCRIPTION
u First-In/First-Out (FIFO) using
Dual-Port Memory
u Advanced CMOS Technology
u High Speed — to 10 ns Access Time
u Asynchronous and Simultaneous
Read and Write
u Fully Expandable by both Word
Depth and/or Bit Width
u Empty and Full Warning Flags
u Half-Full Flag Capability
u Auto Retransmit Capability
u Package Styles Available:
• 28-pin Plastic DIP
• 32-pin Plastic LCC
• 28-pin Ceramic Flatpack
The L8C201, L8C202, L8C203, and
L8C204 are dual-port First-In/First-
Out (FIFO) memories. The FIFO
memory products are organized as:
L8C201 — 512 x 9-bit
L8C202 — 1024 x 9-bit
L8C203 — 2048 x 9-bit
L8C204 — 4096 x 9-bit
Each device utilizes a special algorithm
that loads and empties data on a first-
in/first-out basis. Full and Empty flags
are provided to prevent data overflow
and underflow. Three additional pins
are also provided to allow for unlimited
expansion in both word size and depth.
Depth Expansion does not result in a
flow-through penalty. Multiple devices
are connected with the data and control
signals in parallel. The active device is
determined by the Expansion In (XI)
and Expansion Out (XO) signals which
are daisy chained from device to
device.
L8C201/202/203/204 BLOCK DIAGRAM
DATA INPUTS
D8-0
9
W
WRITE
CONTROL
WRITE
POINTER
RAM ARRAY
512 x 9-bit
1K x 9-bit
2K x 9-bit
4K x 9-bit
READ
POINTER
The read and write operations are
internally sequential through the use
of ring pointers. No address informa-
tion is required to load and unload
data. The write operation occurs
when the Write (W) signal is LOW.
Read occurs when Read (R) goes
LOW. The nine data outputs go to the
high impedance state when R is
HIGH. Retransmit (RT) capability
allows for reset of the read pointer
when RT is pulsed LOW, allowing for
retransmission of data from the
beginning. Read Enable (R) and Write
Enable (W) must both be HIGH
during a retransmit cycle, and then R
is used to access the data. A Half-Full
(HF) output flag is available in the
single device and width expansion
modes. In the depth expansion
configuration, this pin provides the
Expansion Out (XO) information
which is used to tell the next FIFO that
it will be activated.
These FIFOs are designed to have the
fastest data access possible. Even in
lower cycle time applications, faster
access time can eliminate timing
bottlenecks as well as leave enough
margin to allow the use of the devices
without external bus drivers.
The FIFOs are designed for those
applications requiring asychronous
and simultaneous read/writes in
multiprocessing and rate buffer
applications.
R
READ
CONTROL
THREE-STATE
BUFFERS
DATA OUTPUTS
Q8-0
FLAG
EF
LOGIC
FF
EXPANSION
XI
LOGIC
XO/HF
RESET
LOGIC
RS
FL/RT
FIFO Products
1
03/04/99–LDS.8C201/2/3/4-H