L7C108 Datasheet, PDF (1/15 Pages) LOGIC Devices Incorporated – 128K x 8 Static RAM

FEATURES
128K x 8 Static RAM with Chip
Select Powerdown, Output Enable
and Single or Dual Chip Selects
High Speed — to 15 ns maximum
Operational Power, -L Version
Active: 140 mA at 15 ns
Standby: 1 mA max
Data Retention at 2 V for Battery
Backup Operation
Screened to MIL-STD-883, Class B
or to SMD 5962-89598
Package Styles Available:
32-pin Ceramic 400mil DIP D12
32-pin Ceramic LCC K11
32-pin Ceramic SO 1
32-pin uad Ceramic LCC KA1
L7C108
PRELIMINARY INFORMATION L7C109
128K x 8 Static RAM
Pin Configuration
32-pin Ceramic DIP
32-pin Ceramic SOJ
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
VSS ¹⁶
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-pin Quad CLCC
32-pin Ceramic LCC
4 3 2 1 32 31 30
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
Top
View
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 DQ8
14 15 16 17 18 19 20
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 ¹⁵
VSS ¹⁶
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
OVERVIEW
The L7C108 and L7C109 are high-perfor-
mance, low-power CMOS static RAMs.
The storage circuitry is organized as
131,072 words by 8 bits per word. The
8 Data In and Data Out signals share I/O
pins. The L7C108 has a single active-
low Chip Enable. The L7C109 has two
Chip Enables one active-low . These
devices are available in three speeds
with maximum access times from 15 ns
to 45 ns.
Inputs and outputs are TTL compatible.
Operation is from a single +5 V power
supply. Power consumption is 140 mA
-L Version at 15 ns. Data may be
retained in inactive storage with a supply
voltage as low as 2 V.
The L7C108 and L7C109 provide asyn-
chronous unclocked operation with
matching access and cycle times. The
Chip Enables and a three-state I/O bus
with a separate Output Enable control
simplify the connection of several chips
for increased storage capacity.
Memory locations are specified on
address pins A0 through A16. For the
L7C108, reading from a designated
location is accomplished by present-
ing an address and driving CE1 and OE
LOW while WE remains HIGH. For the
L7C109, CE1 and OE must be LOW
while CE2 and WE are HIGH.The data in
the addressed memory location will then
appear on the Data Out pins within one
access time. The output pins stay in a
high-impedance state when CE1 or OE is
HIGH, or CE2 L7C109 or WE is LOW.
Writing to an addressed location is
accomplished when the active-low CE1
and WE inputs are both LOW, and CE2
L7C109 is HIGH. Any of these signals
may be used to terminate the write oper-
ation. Data In and Data Out signals have
the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection cur-
rent of up to 200 mA on any pin without
damage.
LOGIC Devices Incorporated
www.logicdevices.com
1
1M Static RAMs
Aug 11, 2010 LDS-L7C108/9-F