L4C383 Datasheet, PDF (1/11 Pages) LOGIC Devices Incorporated – 16-bit Cascadable ALU (Extended Set)

DEVICES INCORPORATED
DEVICES INCORPORATED
L4C383
L4C383 ^{16-bit Cascadable ALU (Extended Set)}
16-bit Cascadable ALU (Extended Set)
FEATURES
u High-Speed (15ns), Low Power
16-bit Cascadable ALU
u Extended Function Set
(32 Advanced ALU Functions)
u All Registers Have a Bypass Path
for Complete Flexibility
u Replaces IDT7383
u 68-pin PLCC, J-Lead
L4C383 BLOCK DIAGRAM
A15-A0
16
ENA
A REGISTER
FFFFH
DESCRIPTION
The L4C383 is a flexible, high speed,
cascadable 16-bit Arithmetic and Logic
Unit. The L4C383 is capable of
performing up to 32 different
arithmetic or logic functions.
The L4C383 can be cascaded to perform
32-bit or greater operations. See
“Cascading the L4C383” on the next
page.
bit result (F). Five select lines control
the ALU and provide 19 arithmetic and
13 logical functions. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal feed-
back path allows the registered ALU
output to be routed to one or both of
the ALU inputs, accommodating chain
operations and accumulation.
ARCHITECTURE
The L4C383 operates on two 16-bit
operands (A and B) and produces a 16-
ALU OPERATIONS
The S4–S0 lines specify the operation to
be performed. The ALU functions and
their select codes are shown in Table 1.
B15-B0
16
B REGISTER
FFFFH
ALU STATUS
The ALU provides Overflow and Zero
status bits. A Carry output is also
provided for cascading multiple
ENB
devices, however it is only defined for
the 19 arithmetic functions. The ALU
sets the Zero output when all 16 output
bits are zero. The N, C16 and OVF flags
FTAB
for the arithmetic operations are
defined in Table 2.
4
N, C16
OVF, Z
ALU
16
RESULT REGISTER
FTF
OE
CLK
16
TO ALL REGISTERS
16
F15-F0
5
S4-0
C0
ENF
OPERAND REGISTERS
The L4C383 has two 16-bit wide input
registers for operands A and B. These
registers are rising edge triggered by a
common clock. The A register is
enabled for input by setting the ENA
control LOW, and the B register is
enabled for input by setting the ENB
control LOW. When either the ENA
control or ENB control is HIGH, the
data in the corresponding input register
will not change.
This architecture allows the L4C383 to
accept arguments from a single 16-bit
data bus. For those applications that do
not require registered inputs, both the
A and B operand registers can be
bypassed with the FTAB control line.
Arithmetic Logic Units
1
08/16/2000–LDS.383-E