L29C520 Datasheet, PDF (1/8 Pages) LOGIC Devices Incorporated – 4 x 8-bit Multilevel Pipeline Register

DEVICES INCORPORATED
DEVICES INCORPORATED
L29C520/521
4 x 8-bit Mult_Lile₂ve₉l _CPip₅el₂in₀e _/R₅eg₂is₁ter
4 x 8-bit Multilevel Pipeline Register
FEATURES
DESCRIPTION
u Four 8-bit Registers
u Implements Double 2-Stage Pipeline
or Single 4-Stage Pipeline Register
u Hold, Shift, and Load Instructions
u Separate Data In and Data Out Pins
u High-Speed, Low Power CMOS
Technology
u Three-State Outputs
u Replaces IDT29FCT520/IDT29FCT521
and AMD Am29520/Am29521
u Package Styles Available:
• 24-pin PDIP
• 28-pin PLCC, J-Lead
L29C520/521 BLOCK DIAGRAM
The L29C520 and L29C521 are pin-
for-pin compatible with the
IDT29FCT520/IDT29FCT521 and
AMD Am29520/Am29521, imple-
mented in low power CMOS.
The L29C520 and L29C521 contain
four registers which can be configured
as two independent, 2-level pipelines
or as one 4-level pipeline.
The Instruction pins, I1-0, control the
loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the L29C520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
L29C521 differs from the L29C520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I1-0
may be set to prevent any register
from changing.
The S1-0 select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
TABLE 1.
L29C520 INSTRUCTION TABLE
I1 I0 Description
L L D©R1 R1©R2 R2©R3 R3©R4
L H HOLD HOLD D©R3 R3©R4
H L D©R1 R1©R2 HOLD HOLD
H H ALL REGISTERS ON HOLD
TABLE 2.
L29C521 INSTRUCTION TABLE
I1 I0 Description
L L D©R1 R1©R2 R2©R3 R3©R4
L H HOLD HOLD D©R3 HOLD
H L D©R1 HOLD HOLD HOLD
H H ALL REGISTERS ON HOLD
8
D8-0
REG 1
REG 2
REG 3
REG 4
8
Y7-0
OE
2
S1-0
TABLE 3. OUTPUT SELECT
S1 S0 Register Selected
L L Register 4
L H Register 3
H L Register 2
H H Register 1
2
I1-0
CLK
Pipeline Registers
1
08/02/2000–LDS.520/1-P