LTC6915 Datasheet, PDF (9/16 Pages) Linear Technology – Zero Drift, Precision Instrumentation Amplifier with Digitally Programmable Gain

TYPICAL PERFOR A CE CHARACTERISTICS
Settling Time vs Gain
35
V_S = 5V
30
dV_OUT = 1V
0.1% ACCURACY
T_A = 25°C
25
20
15
10
5
0
1
10
100
1000 10000
GAIN (V/V)
6915 G25
Internal Clock Frequency vs
Supply Voltage
3.40
3.35
3.30
T_A = 125°C
3.25
T_A = 85°C
3.20
3.15
T_A = 25°C
T_A = –55°C
3.10
2.5
4.5
6.5
8.5
SUPPLY VOLTAGE (V)
10.5
6915 G26
LTC6915
Additional Gain Error vs Load
Resistance
0.1
0
–0.1
A_V = 16
A_V = 256
–0.2
–0.3
A_V = 4096
–0.4
0
2
4
6
8
LOAD RESISTANCE R_L (k)
10
6915 G27
PI FU CTIO S (DFN/GN Packages)
IN^– (Pin 1/Pin 2): Inverting Analog Input.
SHDN (Pin 1 GN Package Only): Shutdown Pin. The IC is
shut down when SHDN is tied to V⁺. An internal current
source pulls this pin to V^– when floating.
IN⁺ (Pin 2/Pin 3): Noninverting Analog Input.
V^– (Pin 3/Pin 4): Negative Supply.
CS(D0) (Pin 4/Pin 6): TTL Level Input. When in serial
control mode, this pin is the chip select input (active low);
in parallel control mode, this pin is the LSB of the parallel
gain control code.
D_IN(D1) (Pin 5/Pin 7): TTL Level Input. When in serial
control mode, this pin is the serial input data; in parallel
mode, this pin is the second LSB of the parallel gain
control code.
HOLD_THRU (Pin 5 GN Package Only): TTL Level Input
for Parallel Control Mode. When HOLD_THRU is high, the
parallel data is latched in an internal D-latch.
CLK(D2) (Pin 6/Pin 8): TTL Level Input. When in serial
control mode, this pin is the clock of the serial interface; in
parallel mode, this pin is the third LSB of the parallel gain
control code.
D_OUT(D3) (Pin 7/Pin 9): TTL Level Input. When in serial
control mode, this pin is the output of the serial data; in
parallel mode, this pin is the MSB of the 4-bit parallel gain
control code. In parallel mode operation, if the data in to
D_OUT (Pin 9) is from a voltage source greater than V⁺ (Pin
12), then connect a resistor between the voltage source
and D_OUT to limit the current into Pin 9 to 5mA or less.
DGND (Pin 8/Pin 10): Digital Ground.
PARALLEL_SERIAL (Pin 9/Pin 11): Interface Selection
Input. When tied to V⁺, the interface is in parallel mode, i.e.,
the PGA gain is defined by the parallel codes (D3 ~ D0), i.e.,
CS(D0), DATA(D1), CLK(D2), and D_OUT(D3). When
PARALLEL_SERIAL pin is tied to V^–, the PGA gain is set
by the serial interface.
REF (Pin 10/Pin 13): Voltage Reference for PGA output.
OUT (Pin 11/Pin 15): Amplifier Output. The typical current
sourcing/sinking of the OUT pin is 1mA. For minimum gain
error, the load resistance should be 1k or greater (refer to
the Output Voltage Swing vs Output Current and Gain
Error vs Load Resistance in the Typical Performance
Characteristics section).
V⁺ (Pin 12/Pin 16): Positive Supply.
SENSE (Pin 14 GN Package Only): Sense Pin. When the
PGA drives a low resistance load and the interconnect
resistance between the OUT pin and the load is not
negligible, tying the SENSE pin as close as possible to the
load can improve the gain accuracy.
6915f
9