LTC2312-12_15 Datasheet, PDF (9/22 Pages) Linear Technology – 12-Bit, 500ksps Serial Sampling ADC in TSOT

LTC2312-12
Block Diagram
ANALOG SUPPLY
3V OR 5V
2.2µF
1
V_DD
2.5V LDO
2.2µF
I/O INTERFACE SUPPLY
RANGE 1.8V TO 5V
5
OV_DD
ANALOG
INPUT RANGE
0V TO V_REF
A_IN
4
+
S/H
–
12-BIT SAR ADC
2.2µF
REF
2
GND
3
2×/4×
1.024V
BANDGAP
TS8 PACKAGE
ALL CAPACITORS UNLESS
NOTED ARE HIGH QUALITY,
CERAMIC CHIP TYPE
THREE-STATE
SERIAL
OUTPUT
PORT
SDO
6
TIMING
LOGIC
SCK
7
CONV
8
231212 BD
Timing Diagrams
CONV
SDO
t₃
OV_DD/2
Hi-Z
MSB
V_OH
V_OL
Figure 1. SDO Enabled After CONV↓
231312 TD01
SCK
SDO
V_OH
V_OL
t₇
OV_DD/2
Figure 3. SDO Data Valid Hold After SCK↓
231312 TD03
CONV
SDO
t₈
OV_DD/2
Hi-Z
Figure 2. SDO Into Hi-Z After CONV↑
231312 TD02
t₄
SCK
OV_DD/2
V_OH
SDO
V_OL
Figure 4. SDO Data Valid Access After SCK↓
231212 TD04
For more information www.linear.com/LTC2312-12
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