LTC2299 Datasheet, PDF (9/24 Pages) Linear Technology – Dual 14-Bit, 80Msps Low Power 3V ADC

LTC2299
PI FU CTIO S
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to V_DD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNA to V_DD and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to V_DD
and OEA to V_DD results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 V_DD selects offset binary output format and turns the
clock duty cycle stabilizer on. 2/3 V_DD selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
lizer on. V_DD selects 2’s complement output format and
turns the clock duty cycle stabilizer off.
V_CMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to V_CMB.
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to V_CMA selects the internal reference
and a ±0.5V input range. V_DD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±V_SENSEA. ±1V is the largest valid input range.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
W
FUNCTIONAL BLOCK DIAGRA
A_IN+
INPUT
A_IN–
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
V_CM
2.2µF
1.5V
REFERENCE
RANGE
SELECT
REF
SENSE
BUF
SHIFT REGISTER
AND CORRECTION
REFH
REFL INTERNAL CLOCK SIGNALS
DIFF
CLOCK/DUTY
CONTROL
REF
CYCLE
LOGIC
AMP
CONTROL
REFH 0.1µF REFL
2.2µF
1µF
1µF
CLK
MODE SHDN
OE
Figure 1. Functional Block Diagram (Only One Channel is Shown)
OUTPUT
DRIVERS
OV_DD
OF
D13
•
•
•
D0
OGND
2299 F01
2299fa
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