LTC1861L_15 Datasheet, PDF (9/12 Pages) Linear Technology – Power, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP

APPLICATIO S I FOR ATIO
CONV
t_CONV
SCK
DON'T CARE
SLEEP MODE
LTC1860L/LTC1861L
t_SMPL
1 2 3 4 5 6 7 8 9 10 11 12
SDO
Hi-Z
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER
SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC
WILL OUTPUT ZEROS INDEFINITELY
1860 F01
Figure 1. LTC1860L Operating Sequence
111111111111
111111111110
•
•
•
000000000001
000000000000
*V_IN = IN⁺ – IN^–
V_IN*
1860 F02
1µF
V_CC
LTC1860L
1
V_REF
V_IN = 0V TO V_CC ² IN⁺
3 _IN–
8
V_CC
7
SCK
6
SDO
4
GND
5
CONV
1860 F03
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
Figure 2. LTC1860L Transfer Curve
Figure 3. LTC1860L with Rail-to-Rail Input Span
LTC1861L OPERATION
Operating Sequence
The LTC1861L conversion cycle begins with the rising
edge of CONV. After a period equal to t_CONV, the conver-
sion is finished. If CONV is left high after this time, the
LTC1861L goes into sleep mode. The LTC1861L’s 2-bit
data word is clocked into the SDI input on the rising edge
of SCK after CONV goes low. Additional inputs on the SDI
pin are then ignored until the next CONV cycle. The shift
clock (SCK) synchronizes the data transfer with each bit
being transmitted on the falling SCK edge and captured on
the rising SCK edge in both transmitting and receiving
systems. The data is transmitted and received simulta-
neously (full duplex). After completing the data transfer, if
further SCK clocks are applied with CONV low, SDO will
output zeros indefinitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of Table 1. In single-ended
mode, all input channels are measured with respect to
GND (or AGND). A zero code will occur when the “+”
input minus the “–” input equals zero. Full scale occurs
when the “+” input minus the “–” input equals V_REF minus
1LSB. See Figure 5. Both the “+” and “–” inputs are
sampled at the same time so common mode noise is
rejected. The input span in the SO-8 package is fixed at
V_REF = V_CC. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
Reference Input
The reference input of the LTC1861L SO-8 package is
internally tied to V_CC. The span of the A/D converter is
therefore equal to V_CC. The voltage on the reference input
of the LTC1861L MSOP package defines the span of the
A/D converter. The LTC1861L MSOP package can operate
with reference voltages from 1V to V_CC.
18601Lf
9