LTC1773 Datasheet, PDF (9/20 Pages) Linear Technology – Synchronous Step-Down DC/DC Controller

LTC1773
APPLICATIONS INFORMATION
( ) ( ) ^P_SYNC
=
V_IN
– V_OUT
V_IN
I_MAX ² 1+ δ R_DS(ON)
where δ is the temperature dependency of R_DS(ON) and K
is a constant inversely related to the gate drive current.
Both MOSFETs have I²R losses while the topside P-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. The synchronous
MOSFET losses are greatest at high input voltage or during
a short-circuit when the duty cycle in this switch is nearly
100%.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C_RSS is usually specified in the MOSFET
characteristics. The constant K = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.
Typical gate charge for the selected P-channel MOSFET
should be less than 30nC (at 4.5V_GS) while the turn-off
delay should be less than 150ns. However, due to differ-
ences in test and specification methods of various MOSFET
manufacturers, the P-channel MOSFET ultimately should
be evaluated in the actual LTC1773 application circuit to
ensure proper operation.
A Schottky diode can be placed in parallel with the syn-
chronous MOSFET to improve efficiency. It conducts
during the dead-time between the conduction of the two
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on and storing charge
during the dead-time, which could cost as much as 1% in
efficiency. A 1A Schottky is generally a good size for 5A to
8A regulators due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance. The diode may be omit-
ted if the efficiency loss can be tolerated.
C_IN Selection
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle V_OUT/V_IN. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
[ ] ^{( )} _{CIN required}
I_RMS ≅ I_MAX
V_OUT
V_IN – V_OUT
V_IN
12
This formula has a maximum at V_IN = 2V_OUT, where
I_RMS = I_OUT/2. This simple worst-case condition is
commonly used for design because even significant de-
viations do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
C_OUT Selection
The selection of C_OUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (∆V_OUT) is determined by:
∆V_OUT
≅
⎛
∆I_{L⎝⎜}ESR +
1
8fC _OUT
⎞
⎠⎟
where f = operating frequency, C_OUT = output capacitance
and ∆I_L = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆I_L increases
with input voltage. With ∆I_L = 0.4I_OUT(MAX) and allowing
for 2/3 of the ripple due to ESR, the output ripple will be
less than 50mV at max V_IN assuming:
C_OUT required ESR < 2 R_SENSE
C_OUT > 1/(8fR_SENSE)
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran-
tees that the output voltage does not significantly dis-
charge during the operating frequency period due to ripple
current. The choice of using smaller output capacitance
increases the ripple voltage due to the discharging term
but can be compensated for by using capacitors of very
low ESR to maintain the ripple voltage at or below 50mV.
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