LTC1741 Datasheet, PDF(9/20 Page) Linear Technology

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LTC1741 Datasheet, PDF (9/20 Pages) Linear Technology – 12-Bit, 65Msps Low Noise ADC

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BLOCK DIAGRA

LTC1741

AIN+

INPUT

AINâ

S/H

VCM

4.7ÂµF

2.35V

REFERENCE

RANGE

SELECT

REF

SENSE

BUF

FIRST PIPELINED

ADC STAGE

(5 BITS)

DIFF

REF

AMP

SECOND PIPELINED

ADC STAGE

(4 BITS)

THIRD PIPELINED

ADC STAGE

(4 BITS)

REFL

REFH INTERNAL CLOCK SIGNALS

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

CONTROL LOGIC

AND

CALIBRATION LOGIC

TI I G DIAGRA

REFLB REFHA REFLA REFHB ENC ENC

4.7ÂµF

0.1ÂµF

1ÂµF

0.1ÂµF

1ÂµF

MSBINV

Figure 1. Functional Block Diagram

FOURTH PIPELINED

ADC STAGE

(2 BITS)

SHIFT REGISTER

AND CORRECTION

OUTPUT

DRIVERS

OVDD 0.5V TO

D11

CLKOUT

OGND

1741 F01

ANALOG

INPUT

Nâ¢

ENC

DATA

CLKOUT

t11

DATA

DATA (N â 5)

DB11 TO DB0

t12

DATA N

DB11 TO DB0, OF AND CLKOUT

DATA (N â 4)

DB11 TO DB0

DATA (N â 3)

t10

1741 TD

1741f

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