LTC1643L_15 Datasheet, PDF (9/16 Pages) Linear Technology – PCI-Bus Hot Swap Controller

LTC1643L/LTC1643L-1/LTC1643H
APPLICATIONS INFORMATION
LTC1643 FEATURE SUMMARY
1. Allows safe board insertion and removal from either a
motherboard (LTC1643H) or CompactPCI board
(LTC1643L/LTC1643L-1).
2. Controls all four PCI supplies: –12V, 12V, 3.3V and 5V.
3. Programmable foldback current limit: a programmable
analog current limit with a value that depends on the
output voltage. If the output is shorted to ground, the
current limit drops to keep power dissipation and
supply glitches to a minimum.
4. Programmable circuit breaker: if a supply remains in
current limit too long, the circuit breaker will trip, the
supplies will be turned off and the FAULT pin pulled low.
5. Current limit power-up: the supplies are allowed to
power up in current limit. Allows the chip to power up
boards with widely varying capacitive loads without
tripping the circuit breaker. The maximum allowable
power-up time is programmable using the TIMER pin.
6. –12V and 12V power switches on chip.
7. Power good output: monitors the voltage status of the
four supply voltages, except the LTC1643L-1 which
only monitors 3V_OUT and 5V_OUT.
8. Space saving 16-pin SSOP package.
PCI Power Requirements
PCI systems usually require four power rails: 5V, 3.3V,
12V and –12V. Systems implementing the 3.3V signaling
environment are usually required to provide all four rails in
every system. Systems implementing the 5V signaling
environment may either ship the 3.3V supply with the
system or provide a means to add it afterward. The
tolerance of the supplies as measured at the components
on the plug-in card is summarized in Table 1.
Table 1. PCI Power Supply Requirements
SUPPLY TOLERANCE
CAPACITIVE
LOAD
5V
5V ±5%
< 3000µF
3.3V
3.3V ±0.3V
< 3000µF
12V
12V ±5%
< 500µF
– 12V
–12V ±10%
< 120µF
Some ±12V supplies in CompactPCI applications are not
well regulated and can violate the tolerance specification.
For these applications, the LTC1643L-1 should be used
because the PWRGD signal does not depend on ±12V
outputs.
Power-Up Sequence
The power supplies are controlled by placing external
N-channel pass transistors in the 3.3V and 5V power
paths, and internal pass transistors for the 12V and –12V
power paths (Figure 1).
Resistors R1 and R2 provide current fault detection and
R7 and C1 provide current control loop compensation.
Resistors R5 and R6 prevent high frequency oscillations
in Q1 and Q2.
When the ON pin (Pin 5) is pulled high, the pass transistors
are allowed to turn on and a 20µA current source is
connected to the TIMER pin (Pin 4) (Figure 2).
The current in each pass transistor increases until it
reaches the current limit for each supply. Each supply is
then allowed to power up at the rate dv/dt = 50µA/C1 or as
determined by the current limit and the load capacitance
whichever is slower. Current limit faults are ignored while
the TIMER pin (Pin 4) voltage is ramping up and is less
than 0.9V below 12V_IN (Pin 1). Once all four supply
voltages are within tolerance, the PWRGD pin (Pin 7) will
pull low.
Power-Down Sequence
When the ON (Pin 5) is pulled low, a power-down
sequence begins (Figure 3).
Internal switches are connected to each of the output
supply voltage pins to discharge the bypass capacitors to
ground. The TIMER pin (Pin 4) is immediately pulled low.
The GATE pin (Pin 11) is pulled down by a 200µA current
source to prevent the load currents on the 3.3V and 5V
supplies from going to zero instantaneously and glitching
the power supply voltages. When any of the output
voltages dip below its threshold, the PWRGD pin (Pin 7)
pulls high.
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