LTC1418_15 Datasheet, PDF (9/30 Pages) Linear Technology – Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O

BLOCK DIAGRAM
LTC1418
A_IN+
A_IN–
2.5V ^8k
V_REF
2.5V REF
C_SAMPLE
C_SAMPLE
ZEROING SWITCHES
V_DD: 5V
V_SS: 0V FOR UNIPOLAR MODE
– 5V FOR BIPOLAR MODE
REF AMP
14-BIT CAPACITIVE DAC
REFCOMP
AGND
DGND
4.096V
INTERNAL
CLOCK
SUCCESSIVE APPROXIMATION
REGISTER
MUX
CONTROL LOGIC
+
COMP
–
14
SHIFT
REGISTER
•••
D13
D0
D3/(SCLK)
D1/(D_OUT)
D4 (EXTCLKIN) D0 (EXT/INT) SHDN CONVST RD CS SER/PAR D2/(CLKOUT) BUSY
NOTE: PIN NAMES IN PARENTHESES
REFER TO SERIAL MODE
1418 BD
APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1418 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an ana-
log signal to a 14-bit parallel or serial output. The ADC is
complete with a precision reference and an internal clock.
A_IN+
SAMPLE
SAMPLE
A_IN–
C_SAMPLE+
HOLD
C_SAMPLE–
HOLD
ZEROING SWITCHES
HOLD
HOLD
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section
C_DAC+
+
for the data format).
Conversion start is controlled by the CS and CONVST
V_DAC+
C_DAC–
COMP
–
inputs. At the start of the conversion the successive ap-
proximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
V_DAC–
SAR
14
OUTPUT
LATCH
D13
D0
1418 F01
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
Figure 1. Simplified Block Diagram
most significant bit (MSB) to the least significant bit (LSB).
For more information www.linear.com/LTC1418
1418fa
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