LT6553_15 Datasheet, PDF (9/12 Pages) Linear Technology – 650MHz Gain of 2 Triple Video Amplifier

LT6553
APPLICATIO S I FOR ATIO
If the AGND pins are not connected directly to a low
impedance ground plane, they must be carefully bypassed
to maintain minimal impedance over frequency. Pin 6 is a
shared connection of the gain resistors of both channel G
and channel B, and any resistance external to this node can
significantly decrease the isolation between those chan-
nels. Although crosstalk will be very dependent on the
board layout, a recommended starting point for bypass
capacitors would be 470pF as close as possible to each
AGND pin with one 4700pF capacitor in parallel.
To maintain the LT6553’s channel isolation, it is beneficial
to shield parallel input and output traces using a ground
plane or power supply traces. Vias between topside and
backside metal may be required to maintain a low
inductance ground near the part where numerous traces
converge.
ESD Protection
The LT6553 has reverse-biased ESD protection diodes on
all pins. If any pins are forced a diode drop above the
positive supply or a diode drop below the negative supply,
large currents may flow through these diodes. If the
current is kept below 10mA, no damage to the devices will
occur.
TYPICAL APPLICATIO
RGB Buffer Demo Board
The DC714 Demo Board illustrates optimal routing,
bypassing and termination using the LT6553 as an
RGB video buffer. The schematic is shown in Figure 1. All
inputs and outputs are routed to have a characteristic
impedance of 75Ω and 75Ω input shunt and output series
terminations are connected as close to the part as pos-
sible. For ideal operation, a 75Ω load termination should
be connected at the output. The LT6553’s gain of 2 will
compensate for the resulting divider between the series
and load termination resistors.
E1
EN
J1
50Ω BNC
1
EN
JP1
CONTROL
5432
12 3
ENABLE EXT
JP2
DGND
12 3
E2
AGND FLOAT DGND
5 ^{BNC × 3}
INR 4
1 Z = 75
3
2 J5
5
ING 4
Z = 75
1
3
2 J6
5
Z = 75
INB 4
1
3
2 J7
R4
R5
R6
75Ω 75Ω 75Ω
1 _EN
LT6553
V^{+ 16}
2 _DGND
V^{+ 15}
3
INR
14
OUTR
4
AGND
V^{– 13}
5
ING
12
OUTG
6 _AGND
V^{+ 11}
7 _INB
OUTB ¹⁰
8 _V–
V^{– 9}
C1
4700pF
C2
470pF
R1
75Ω
R2
75Ω
R3
75Ω
E3
AGND
AGND
J3
BANANA
5 ^JACK
CAL 4
1
3
2 J8
BNC
SINGLE DUAL
1 ²³
JP3
SUPPLY
C5
470pF
C6
1000pF
C7
470pF
C8
4700pF
C9
10µF, 16V
1210
Figure 1. DC714 Demo Board Schematic
C3
4700pF
Z = 75
Z = 75
Z = 75
Z = 75
V⁺
V⁺
C4
J2
10µF, 16V BANANA
1210
JACK
NOTE 5
BNC x3 ₅
1
4
3
J9 2
5
1
4
3
J10 2
5
1
4
3
J11 2
V^–
V^–
J4
BANANA JACK
OUTR
OUTG
OUTB
5
1
4 CAL
3
J12 2
BNC
6553 F01
6553f
9