LT3501_15 Datasheet, PDF (9/30 Pages) Linear Technology – Monolithic Dual Tracking 3A Step-Down Switching Regulator

LT3501
Pin Functions
the clock signal is detected, with switch 1 in phase with
the synchronization signal. Each rising clock edge initiates
an oscillator ramp reset. A gain control loop servos the
oscillator charging current to maintain a constant oscillator
amplitude. Hence, the slope compensation and channel
phase relationship remain unchanged. If the clock signal
is removed, the oscillator reverts to resistor mode and
reapplies the 0.975V bias to the R_T/SYNC pin after the
synchronization detection circuitry times out. The clock
source impedance should be set such that the current out
of the R_T/SYNC pin in resistor mode generates a frequency
roughly equivalent to the synchronization frequency.
BST1/BST2 (Pins 20, 11): The BST pin provides a higher
than V_IN base drive to the power NPN to ensure a low
switch drop. A comparator to V_IN imposes a minimum
off-time on the SW pin if the BST pin voltage drops too
low. Forcing a SW off-time allows the boost capacitor to
recharge.
Exposed Pad (Pin 21): GND. The Exposed Pad GND pin is
the only ground connection for the device. The Exposed
Pad should be soldered to a large copper area to reduce
thermal resistance. The GND pin is common to both chan-
nels and also serves as small-signal ground. For ideal
operation all small-signal ground paths should connect
to the GND pin at a single point, avoiding any high current
ground returns.
3501fd
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