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LTC4403-1_15 Datasheet, PDF (8/12 Pages) Linear Technology – Multiband RF Power Controllers for EDGE/TDMA
LTC4403-1/LTC4403-2
APPLICATIO S I FOR ATIO
Determining External Loop Gain and Bandwidth
The external loop voltage gain contributed by the RF chan-
nel and coupler network should be measured in a closed
loop configuration. A voltage step is applied to PCTL and
the change in VPCA (or VPCB) is measured. The detected RF
voltage is 0.6 • PCTL and the external voltage gain contrib-
uted by the RF power amplifier and coupler network is
0.6 • ∆VPCTL/∆VVPCA. Measuring voltage gain in the closed
loop configuration accounts for the nonlinear detector
gain that is dependent on RF input voltage and frequency.
The LTC4403-X unity gain bandwidth specified in the data
sheet assumes that the net voltage gain contributed by the
RF power amplifier and coupler network is unity. The
bandwidth is calculated by measuring the rise time be-
tween 10% and 90% of the voltage change at VPCA or VPCB
for a small step in voltage applied to PCTL.
BW1 = 0.35/rise time
The LTC4403-X control amplifier unity gain bandwidth
(BW1) is typically 250kHz. For PCTL <100mV the phase
margin of the control amplifier is typically 90°.
For PCTL voltages <100mV, the RF detected voltage is
0.6PCTL. For PCTL voltages >200mV, RF detected voltage
is 1.22PCTL – 0.1. This change in gain is due to an internal
compression circuit designed to extend the detector range.
For example, to determine the external RF channel loop
voltage gain with the loop closed, apply a 100mV step to
PCTL from 0mV to 100mV. VPCA (or VPCB) will increase to
supply enough feedback voltage to the RF pin to cancel
this 100mV step which would be the required detected
voltage of 60mV. Suppose that VPCA changed from 1.498V
to 1.528V to create the RF output power change required.
The net external voltage gain contributed by the RF power
amplifier and directional coupler network can be calcu-
lated by dividing the 60mV change at the RF pin by the
30mV change at the VPCA pin. The net external voltage gain
would then be approximately 2. The loop bandwidth
extends to 2 • BW1. If BW1 is 250kHz, the loop bandwidth
increases to approximately 0.5MHz. The phase margin
can be determined from Figures 2 and 3. Repeat the
above voltage gain measurement over the full power and
frequency range.
External pole frequencies within the loop will further
reduce phase margin. The phase margin degradation, due
to external and internal pole combinations, is difficult to
determine since complex poles are present. Gain peaking
may occur, resulting in higher bandwidth and lower phase
margin than predicted from the open loop Bode plot. A low
frequency AC SPICE model of the LTC4403-X power
controller is included (Figures 6 and 7) to better determine
pole and zero interactions. The user can apply external
gains and poles to determine bandwidth and phase mar-
gin. DC, transient and RF information cannot be extracted
from this model. The model is suitable for external gain
evaluations up to 6 ×. The 270kHz PCTL input filter limits
the bandwidth; therefore, use the RF input as demon-
strated in the model.
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
100
180
RLOAD = 400Ω 160
CLOAD = 33pF 140
120
PHASE
100
80
60
GAIN
40
20
0
–20
–40
–60
–80
–100
1k 10k 100k 1M 10M
FREQUENCY (Hz)
4403 F02
Figure 2. Measured Open Loop Gain and Phase, PCTL <100mV
8
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
100
180
RLOAD = 400Ω
CLOAD = 33pF
160
140
120
PHASE
100
80
60
GAIN
40
20
0
–20
–40
–60
–80
–100
1k 10k 100k 1M 10M
FREQUENCY (Hz)
4403 F03
Figure 3. Measured Open Loop Gain and Phase, PCTL >200mV
4403f