LTC4253_15 Datasheet, PDF (8/34 Pages) Linear Technology – 48V Hot Swap Controllers with Sequencer

LTC4253/LTC4253A
TYPICAL PERFORMANCE CHARACTERISTICS
I_PGH vs Temperature
60
I_IN = 2mA
58 V_PWRGD = 0V
56
54
52
50
48
46
44
42
40
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G28
t_SS vs Temperature
300
I_IN = 2mA
290 SS PIN FLOATING
280 ^{VSS RAMPS FROM 0.2V TO 2V}
270
260
250
240
230
220
210
200
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G29
t_SQ vs Temperature
500
I_IN = 2mA
450 V_SQTMR RAMPS FROM 0.5V TO 3.5V
400
350
300
250
200
150
100
50
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G30
PIN FUNCTIONS
EN2 (Pin 1): Power Good Status Output Two Enable. This
is a TTL compatible input that is used to control PWRGD2
and PWRGD3 outputs. When EN2 is driven low, both
PWRGD2 and PWRGD3 will go high. When EN2 is driven
high, PWRGD2 will go low provided PWRGD1 has been
active for more than one power good sequence delay
(t_SQT) provided by the sequencing timer. EN2 can be used
to control the power good sequence. This pin is internally
pulled low by a 120µA current source.
PWRGD2 (Pin 2): Power Good Status Output Two. Power
good sequence starts with PWRGD1 latching active low.
PWRGD2 will latch active low after EN2 goes high and
after one power good sequence delay t_SQT provided by
the sequencing timer from the time PWRGD1 goes low,
whichever comes later. PWRGD2 is reset by PWRGD1
going high or EN2 going low. This pin is internally pulled
high by a 50µA current source.
PWRGD1 (Pin 3): Power Good Status Output One. At start-
up, PWRGD1 latches active low and starts the power good
sequence when the DRAIN pin is below 2.39V and GATE
is within 2.8V of V_IN. PWRGD1 status is reset by UV, V_IN
(UVLO), RESET going high or circuit breaker fault time-out.
This pin is internally pulled high by a 50µA current source.
V_IN (Pin 4): Positive Supply Input. Connect this pin to the
positive side of the supply through a dropping resistor. A
shunt regulator clamps V_IN at 13V above V_EE. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the V_IN pin is greater than V_LKO, overriding UV and OV. If
UV is high, OV is low and V_IN comes out of UVLO, TIMER
starts an initial timing cycle before initiating GATE ramp
up. If V_IN drops below approximately 8.2V (8.5V for the
LTC4253A), GATE pulls low immediately.
RESET (Pin 5): Circuit Breaker Reset Pin. This is an asyn-
chronous TTL compatible input. RESET going high will pull
GATE, SS, TIMER, SQTIMER low and the PWRGD outputs
high. The RESET pulse must be wide enough to discharge
any voltage on the TIMER pin below V_TMRL. After the reset
of a latched fault, the chip waits for the interlock conditions
before recovering as described in Interlock Conditions in
the Operation section.
SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush
current during start up, thereby effecting control over di/dt.
A 20X attenuated version of the SS pin voltage is presented
to the current limit amplifier. This attenuated voltage limits
the MOSFET’s drain current through the sense resistor
during the soft-start current limiting. At the beginning of
425353aff
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