LTC4150 Datasheet, PDF (8/12 Pages) Linear Technology – Coulomb Counter/ Battery Gas Gauge

LTC4150
APPLICATIO S I FOR ATIO
INT, POL and CLR
INT asserts low each time the LTC4150 measures a unit of
charge. At the same time, POL is latched to indicate the
polarity of the charge unit. The integrator and counter
continue running, so the microcontroller must service and
clear the interrupt before another unit of charge accumu-
lates. Otherwise, one measurement will be lost. The time
available between interrupts is the reciprocal of
Equation 2:
Time per INT Assertion =
1
(9)
G_VF •⏐V_SENSE⏐
At 50mV full scale, the minimum time available is 596ms.
To be conservative and accommodate for small, unex-
pected excursions above the 50mV sense voltage limit, the
microcontroller should process the interrupt and polarity
information and clear INT within 500ms.
Toggling CLR low for at least 20µs resets INT high and
unlatches POL. Since the LTC4150’s integrator and counter
operate independently of the INT and POL latches, no
charge information is lost during the latched period or
while CLR is low. Charge/discharge information continues
to accumulate during those intervals and accuracy is
unaffected.
Once cleared, INT idles in a high state and POL indicates
real-time polarity of the battery current. POL high indi-
cates charge flowing into the battery and low indicates
charge flowing out. Indication of a polarity change re-
quires at least:
t_POL
=
G_VF
•
2
1024 •⏐V_SENSE⏐
(10)
where V_SENSE is the smallest sense voltage magnitude
before and after the polarity change.
Open-drain outputs POL and INT can sink I_OL = 1.6mA at
V_OL = 0.5V. The minimum pull-up resistance for these pins
should be:
R_L > (V_CC – 0.5) / 1.6mA
(11)
where V_CC is the logic supply voltage. Because speed isn’t
an issue, pull-up resistors of 10k or higher are adequate.
8
Interfacing to INT, POL, CLR and SHDN
The LTC4150 operates directly from the battery, while in
most cases the microcontroller supply comes from some
separate, regulated source. This poses no problem for INT
and POL because they are open-drain outputs and can be
pulled up to any voltage 9V or less, regardless of the
voltage applied to the LTC4150’s V_DD.
CLR and SHDN inputs require special attention. To drive
them, the microcontroller or external logic must generate
a minimum logic high level of 1.9V. The maximum input
level for these pins is V_DD + 0.3V. If the microcontroller’s
supply is more than this, resistive dividers must be used
on CLR and SHDN. The schematic in Figure 6 shows an
application with INT driving CLR and microcontroller V_CC
> V_DD. The resistive dividers on CLR and SHDN keep the
voltages at these pins within the LTC4150’s V_DD range.
Choose R2 and R1 so that:
(R1 + R2) ≥ 50R_L
(12)
1.9V
≤
R1
R1+ R2
V_CC
≤
V_DD
(Minimum)
(13)
Equation 13 also applies to the selection of R3 and R4. The
minimum V_DD is the lowest supply to the LTC4150 when
the battery powering it is at its lowest discharged voltage.
When the battery is removed in any application, the CLR
and SHDN inputs are unpredictable. INT and POL outputs
may be erratic and should be ignored until after the battery
is replaced.
If desired, the simple logic of Figure 4 may be used to
derive separate charge and discharge pulse trains from
INT and POL.
INT
CHARGE
CLR
LTC4150
DISCHARGE
POL
4150 F04
Figure 4. Unravelling Polarity—
Separate Charge and Discharge Outputs
4150fa