LTC4110 Datasheet, PDF (8/52 Pages) Linear Technology – Battery Backup System Manager

LTC4110
PIN FUNCTIONS
DCIN (Pin 1): External DC Power Sense Input. Provides a
control input and supply for the main supply ideal diode
function.
CLN (Pin 2): Current Limit Sense Negative Input. See
CLP pin.
CLP (Pin 3): Current Limit Sense Positive Input. This pin
and the CLN pin form a differential input that senses volt-
age on an external resistor for reverse current entering the
power source while in low loss calibration mode. Should
the current approach reversal, this function will terminate
calibration. An RC filter may be required to filter out system
load noise. Connect both CLP and CLN pins to GND to
disable this function. A differential voltage of >1V between
the CLP and CLN pins may damage the device.
ACPDLY (Pin 4): ACPb Delay Control Pin. A capacitor
connected from ACPDLY to GND and a resistor from
V_REF to GND programs delay in the ACPb pin high-to-low
transition. Open if minimum delay is desired.
DCDIV (Pin 5): AC Present Detection Input. Backup
operation is invoked when the system power voltage,
divided by an external resistor divider, falls below the
threshold of this pin.
SHDN (Pin 6): Active High Shutdown/Reset Control Logic
Input. Forces micropower shutdown mode if high when
DCIN supply is removed. Forces all registers to reset if high
when DCIN supply is present. Normally tied to ground.
Internal pin pull-up current.
SDA (Pin 7): SMBus Bidirectional Data Signal. Connect
to V_DD when not in use.
SCL (Pin 8): SMBus Clock Signal Input From SMBus Host.
Connect to V_DD when not in use.
GPIO1 (Pin 9): General Purpose I/O or Charge Status Pin. A
logic-level I/O bit port that is configurable as a host-driven
input/output port or as a battery charge status output (CHGb)
with an open-drain N-MOSFET that is asserted low when any
smart battery or Li-Ion battery is in any phase of charging
or when lead acid battery charge current is >C/x where:
x= ^C •5
I_CHG
(See C/x Charge Termination section for more details).
If the No SMBus option is selected with the SELA pin,
the GPIO1 pin defaults as battery charge status. Refer
to Table 5a.
GPIO2 (Pin 10): General Purpose I/O Pin. A logic-level I/O bit
port that is configurable as a host-driven input/output port
or as a battery undervoltage status output (BKUP_FLTb)
with an open-drain N-MOSFET that is asserted low only
while in backup mode if the battery’s average cell voltage
drops below voltage programmed by the V_DIS pin. If the
No SMBus option is selected with the SELA pin, then the
GPIO2 pin defaults as battery undervoltage status. Refer
to Table 5c.
GPIO3 (Pin 11): General Purpose I/O Pin. A logic-level I/O
bit port that is configurable as a host-driven input/output
port or as a calibration complete status output (CAL_COM-
PLETEb) with an open-drain N-MOSFET that is asserted
low when calibration has been completed. If the SELA pin
is programmed for no SMBus use then the status output
is charge fault (CHGFLTb) instead of calibration complete.
Refer to Table 5e.
SELA (Pin 12): SMBus Address Selection Input. Selects
the LTC4110 SMBus address to facilitate redundant backup
systems when standard batteries are used. Connect to
GND for 12h, V_DD for 28h and the V_REF pin for 20h. When
a smart battery is selected by the TYPE pin, the SELA pin
must be connected to GND to select address 12h. If the
SMBus is not used or to force all GPIOs to status mode
upon power-up, connect pin to a typically 0.5 • V_REF volt-
age from V_REF pin resistor divider. The SMBus address,
if used, will be 12h.
4110fa
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