LTC3873-5 Datasheet, PDF (8/16 Pages) Linear Technology – No RSENSETM Constant Frequency Current Mode Boost/Flyback/SEPIC DC/DC Controller

LTC3873-5
OPERATION
V_TURNON (nominally 4.1V) at least momentarily to enable
LTC3873-5 operation. The V_CC voltage is then allowed to fall
to V_TURNOFF (nominally 2.9V) before undervoltage lockout
disables the LTC3873-5. The RUN/SS pin can be driven
below V_SHDN (nominally 0.7V) to force the LTC3873-5 into
shutdown. When the chip is off, the input supply current is
typically only 50μA. Keep in mind that V_CC should exceed
the gate threshold voltage of the switching MOSFET for
safe operation.
Soft-Start
Leave the RUN/SS pin open to use the internal 3.3ms
soft-start. During the internal soft-start, a voltage ramp
limits the V_ITH. 3.3ms is required for I_TH to ramp from
zero current level to full current level. The soft-start can
be lengthened by placing an external capacitor from the
RUN/SS pin to the GND. A 3μA current will charge the
capacitor, pulling the RUN/SS pin above the shutdown
threshold and a 15μA pull-up current will continue to ramp
RUN/SS to limit V_ITH during the start-up. When RUN/SS
is driven by an external logic, a minimum of 2.75V logic
is recommended to allow the maximum I_TH range.
Light Load Operation
Under very light load current conditions, the I_TH pin voltage
will be very close to 0.85V. As the load current decreases
further, an internal offset at the current comparator input
will assure that the current comparator remains tripped
(even at zero load current) and the regulator will start to
skip cycles in order to maintain regulation. This behavior
allows the regulator to maintain constant frequency down
to very light loads, resulting in low output ripple as well
as low audible noise and reduced RF interference while
providing high light load efficiency.
Current Sense
During the switch on-time, the control circuit limits the
maximum voltage drop across the current sense com-
ponent to about 295mV, 110mV and 185mV at low duty
cycle with IPRG tied to V_IN, GND or left floating respec-
tively. It is reduced with increasing duty cycle as shown
in Figure 4.
300
250
IPRG = HIGH
200
IPRG = FLOAT
150
IPRG = LOW
100
50
0
1
20
40
60
80
100
DUTY CYCLE (%)
3873-5 F04
Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle
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