LTC3869 Datasheet, PDF (8/40 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down DC/DC Controllers

LTC3869/LTC3869-2
PIN FUNCTIONS (UFD/GN)
RUN1, RUN2 (Pin 27, Pin 10/Pin 1, Pin 13): Run Control
Inputs. A voltage above 1.2V on either pin turns on the IC.
However, forcing either of these pins below 1.2V causes
the IC to shut down the circuitry required for that particular
channel. There are 1µA pull-up currents for these pins.
Once the RUN pin raises above 1.2V, an additional 4.5µA
pull-up current is added to the pin.
V_FB1, V_FB2 (Pin 4, Pin 5/Pin 4, Pin 10): Error Amplifier
Feedback Inputs. These pins receive the remotely sensed
feedback voltages for each channel from external resistive
dividers across the outputs.
I_TH1, I_TH2 (Pin 3, Pin 6/Pin 6, Pin 8): Current Control
Thresholds and Error Amplifier Compensation Points.
Each associated channels’ current comparator tripping
threshold increases with its I_TH control voltage.
SGND (Pin 29/Pin 7): Signal Ground. All small-signal
components and compensation components should con-
nect to this ground, which in turn connects to PGND at
one point. Pin 29 is the exposed pad, only available for
the UFD package. The exposed pad must be soldered to
PCB ground for electrical connection and rated thermal
performance.
TK/SS1, TK/SS2 (Pin 2, Pin 7/Pin 5, Pin 9): Output Volt-
age Tracking and Soft-Start Inputs. When one particular
channel is configured to be the master of two channels,
a capacitor to ground at this pin sets the ramp rate for
the master channel’s output voltage. When the channel
is configured to be the slave of two channels, the V_FB
voltage of the master channel is reproduced by a resistor
divider and applied to this pin. Internal soft-start currents
of 1.2µA are charging these pins.
MODE/PLLIN (Pin 25/Pin 27): Forced Continuous Mode,
Burst Mode Operation, or Pulse-Skipping Mode Selection
Pin and External Synchronization Input to Phase Detec-
tor Pin. Connect this pin to SGND to force both channels
in continuous mode of operation. Connect to INTV_CC to
enable pulse-skipping mode of operation. Leave the pin
floating will enable Burst Mode operation. A clock on
the pin will force the controller into continuous mode of
operation and synchronize the internal oscillator with the
clock on this pin. The PLL compensation components are
integrated inside the IC.
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FREQ (Pin 26/Pin 28): There is a precision 10µA current
flowing out of this pin. Connect a resistor to ground set
the controllers’ operating frequency. Alternatively, this pin
can be driven with a DC voltage to vary the frequency of
the internal oscillator.
I_LIM (Pin 11/NA): Current Comparator Sense Voltage Range
Inputs. This pin is to be programmed to SGND, FLOAT
or INTV_CC to set the maximum current sense threshold
to three different levels for each comparator. The current
limit default value is set to be 50mV for LTC3869GN-2.
EXTV_CC (Pin 12/Pin 14): External Power Input to an Inter-
nal Switch Connected to INTV_CC. This switch closes and
supplies the IC power, bypassing the internal low dropout
regulator, whenever EXTV_CC is higher than 4.7V. Do not
exceed 6V on this pin.
V_IN (Pin 20/Pin 22): Main Input Supply. Decouple this pin
to PGND with a capacitor (0.1µF to 1µF).
BOOST1, BOOST2 (Pin 22, Pin 16/Pin 24, Pin 18): Boosted
Floating Driver Supplies. The (+) terminal of the booststrap
capacitors connect to these pins. These pins swing from
a diode voltage drop below INTV_CC up to V_IN + INTV_CC.
TG1, TG2 (Pin 23, Pin 15/Pin 25, Pin 17): Top Gate
Driver Outputs. These are the outputs of floating drivers
with a voltage swing equal to INTV_CC superimposed on
the switch nodes voltages.
SW1, SW2 (Pin 24, Pin 14/Pin 26, Pin 16): Switch Node
Connections to Inductors. Voltage swing at these pins
is from a Schottky diode (external) voltage drop below
ground to V_IN.
SENSE1⁺, SENSE2⁺ (Pin 28, Pin 9/Pin 2, Pin 12): Current
Sense Comparator Inputs. The (+) inputs to the current
comparators are normally connected to DCR sensing
networks or current sensing resistors.
SENSE1^–, SENSE2^– (Pin 1, Pin 8/Pin 3, Pin 11): Current
Sense Comparator Inputs. The (–) inputs to the current
comparators are connected to the outputs.
PGND (Pin 17/Pin 19): Power Ground Pin. Co nnect this pin
closely to the sources of the bottom N-channel MOSFETs,
the (–) terminal of CV_CC and the (–) terminal of C_IN.
BG1, BG2 (Pin 21, Pin 18/Pin 23, Pin 20): Bottom Gate
Driver Outputs. These pins drive the gates of the bottom
N-channel MOSFETs between PGND and INTV_CC.
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