LTC2314-14_15 Datasheet, PDF (8/22 Pages) Linear Technology – 14-Bit, 4.5Msps Serial Sampling ADC in TSOT

LTC2314-14
TYPICAL PERFORMANCE CHARACTERISTICS T_A = 25°C, V_DD = 5V, OV_DD = 2.5V, f_SMPL = 4.5Msps,
unless otherwise noted.
Supply Current (I_VDD)
vs Supply Voltage (V_DD)
6.50
6.25
5Msps
6.00 _5Msps
5.75 ^{fSCK = 87.5MHz}
5.50
5.25
5.00
3Msps
f_SCK = 52.5MHz
4.75
OPERATION
NOT ALLOWED
3Msps
4.50
2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3
SUPPLY VOLTAGE (V)
231414 G17
Output Supply Current (I_OVDD)
vs Output Supply Voltage (OV_DD)
2.5
2.0
1.5
5Msps
f_SCK = 87.5MHz
1.0
3Msps
0.5
f_SCK = 52.5MHz
0
1.7 2.3 2.9 3.5 4.1 4.7 5.3
OUTPUT SUPPLY VOLTAGE (V)
231414 G18
PIN FUNCTIONS
V_DD (Pin 1): Power Supply. The ranges of V_DD are 2.7V
to 3.6V and 4.75V to 5.25V. Bypass V_DD to GND with a
2.2µF ceramic chip capacitor.
REF (Pin 2): Reference Input/Output. The REF pin volt-
age defines the input span of the ADC, 0V to V_REF. By
default, REF is an output pin and produces a reference
voltage V_REF of either 2.048V or 4.096V depending on
V_DD (see Table 2). Bypass to GND with a 2.2µF, low ESR,
high quality ceramic chip capacitor. The REF pin may be
overdriven with a voltage at least 50mV higher than the
internal reference voltage output.
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
A_IN (Pin 4): Analog Input. A_IN is a single-ended input with
respect to GND with a range from 0V to V_REF.
OV_DD (Pin 5): I/O Interface Digital Power. The OV_DD range
is 1.71V to 5.25V. This supply is nominally set to the
same supply as the host interface (1.8V, 2.5V, 3.3V or
5V). Bypass to GND with a 2.2µF ceramic chip capacitor.
SDO (Pin 6): Serial Data Output. The A/D conversion result
is shifted out on SDO as a serial data stream with the MSB
first through the LSB last. There is 1 cycle of conversion
latency. Logic levels are determined by OV_DD.
SCK (Pin 7): Serial Data Clock Input. The SCK serial clock
falling edge advances the conversion process and outputs
a bit of the serialized conversion result, MSB first to LSB
last. SDO data transitions on the falling edge of SCK. A
continuous or burst clock may be used. Logic levels are
determined by OV_DD.
CS (Pin 8): Chip Select Input. This active low signal starts
a conversion on the falling edge and frames the serial data
transfer. Bringing CS high places the sample-and-hold
into sample mode and also forces the SDO pin into high
impedance. Logic levels are determined by OV_DD.
231414fa
8
For more information www.linear.com/LTC2314-14