LTC2239 Datasheet, PDF (8/24 Pages) Linear Technology – 10-Bit, 80Msps Low Noise 3V ADC

LTC2239
PI FU CTIO S
A_IN+ (Pin 1): Positive Differential Analog Input.
A_IN- (Pin 2): Negative Differential Analog Input.
REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
V_DD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V_DD results in normal operation with the
outputs at high impedance. Connecting SHDN to V_DD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V_DD and OE to V_DD
results in sleep mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
NC (Pins 12 to 15): Do Not Connect These Pins.
D0 – D9 (Pins 16, 17, 18, 19, 22, 23, 24, 25, 26, 27):
Digital Outputs. D9 is the MSB.
OGND (Pin 20): Output Driver Ground.
OV_DD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1µF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 V_DD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 V_DD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. V_DD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to V_CM selects the internal reference and a ±0.5V
input range. V_DD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±V_SENSE. ±1V is the largest valid input range.
V_CM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
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