LTC2159 Datasheet, PDF (8/32 Pages) Linear Technology – 16-Bit, 20Msps Low Power ADC

LTC2159
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V_DD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V_DD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V_DD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: V_DD = OV_DD = 1.8V, f_SAMPLE = 20MHz, LVDS outputs, differential
ENC⁺/ENC^– = 2V_P-P sine wave, input range = 2V_P-P with differential drive,
unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: V_DD = 1.8V, f_SAMPLE = 20MHz, CMOS outputs, ENC⁺ = single-
ended 1.8V square wave, ENC^– = 0V, input range = 2V_P-P with differential
drive, 5pF load on each digital output unless otherwise noted.
Note 10: Recommended operating conditions.
Timing Diagrams
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
ANALOG
INPUT
ENC^–
ENC⁺
D0–D15, OF
CLKOUT⁺
CLKOUT ^–
t_AP
N
t_H
N+1
t_L
N+2
N+3
N+4
t_D
N–6
t_C
N–5
N–4
N–3
N–2
2159 TD01
2159f
8