LTC1655LCS8 Datasheet, PDF (8/16 Pages) Linear Technology – 16-Bit Rail-to-Rail Micropower DACs in

LTC1655/LTC1655L
PIN FUNCTIONS
CLK (Pin 1): The TTL Level Input for the Serial Interface
Clock.
D_IN (Pin 2): The TTL Level Input for the Serial Interface
Data. Data on the D_IN pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1655/LTC1655L requires a 16-bit word.
CS/LD (Pin 3): The TTL Level Input for the Serial Inter-
face Enable and Load Control. When CS/LD is low, the
CLK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.
D_OUT (Pin 4): Output of the Shift Register. Becomes valid
on the rising edge of the serial clock and swings from GND
to V_CC.
GND (Pin 5): Ground.
REF (Pin 6): Reference. Output of the internal reference is
2.048V (LTC1655), 1.25V (LTC1655L). There is a gain of
two from this pin to the output. The reference can be
overdriven from 2.2V to V_CC/2 (LTC1655) and 1.3V to
V_CC/2 (LTC1655L). When tied to V_CC/2, the output will
swing from GND to V_CC. The output can only swing to
within its offset specification of V_CC (see Applications
Information).
V_OUT (Pin 7): Deglitched Rail-to-Rail Voltage Output. V_OUT
clears to 0V on power-up.
V_CC (Pin 8): Positive Supply Input. 4.5V ≤ V_CC ≤ 5.5V
(LTC1655), 2.7V ≤ V_CC ≤ 5.5V (LTC1655L). Requires a
0.1µF bypass capacitor to ground.
WU
W
TI I G DIAGRA
t₉
t₁
t₇
t₂
t₄
t₃
t₆
CLK
1
2
3
15
16
D_IN
D15
MSB
D14
D13
CS/LD
D_OUT
t₈
D15
PREVIOUS WORD
D14
D13
PREVIOUS WORD PREVIOUS WORD
D1
D0
LSB
t₅
D0
PREVIOUS WORD
D15
CURRENT WORD
1655/55L TD
8