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LTC1472 Datasheet, PDF (8/16 Pages) Linear Technology – Protected PCMCIA VCC and VPP Switching Matrix
LTC1472
U
OPERATION
VCC XOR Input Circuitry
The LTC1472 ensures that the 3.3V and 5V switches are
never turned on at the same time by employing an XOR
function which locks out the 3.3V switch when the 5V
switch is turned on, and locks out the 5V switch when the
3.3V switch is turned on. This XOR function also makes it
possible for the LTC1472 to work with either active-low or
active-high PCMCIA VCC switch control logic (see Applica-
tions Information for further details).
to ground. Both switches also have independent thermal
shutdown which limits the power dissipation to safe
levels.
VCC Switch Truth Table
VCC EN0
0
1
0
1
VCC EN1
0
0
1
1
VCC(OUT)
OFF
5V
3.3V
OFF
VCC Break-Before-Make Switch Control
The LTC1472 has built-in delays to ensure that the 3.3V
and 5V switch are non-overlapping. Further, the gate
charge pumps include circuity which ramps the NMOS
switches on slowly (400µs typical rise time) but turn off
much more quickly (typically 10µs).
VCC Bias, Oscillator and Gate Charge Pump
When either the 3.3V or 5V switch is enabled, a bias
current generator and high frequency oscillator are turned
on. An on-chip capacitive charge pump generates ap-
proximately 12V of gate drive for the internal low RDS(ON)
NMOS VCC switches from the 5VIN power supply. There-
fore, an external 12V supply is not required to switch the
VCC output. The 5VIN supply current drops below 1µA
when both switches are turned off.
VCC Gate Charge and Discharge Control
Both VCC switches are designed to ramp on slowly (400µs
typical rise time). Turn off time is much quicker
(typically 10µs).
To ensure that both VCC NMOS switch gates are fully
discharged, program the switch to the high impedance
mode at least 100µs before turning off the 5VIN power
supply.
VCC Switch Protection
Two levels of protection are designed into each of the
power switches in the LTC1472. Both VCC switches are
protected against accidental short circuits with SafeSlot
fold-back current limit circuits which limit the output
current to typically 1A when the VCC(OUT) output is shorted
THE VPP SWITCHING SECTION
The VPP switching section of the LTC1472 consists of the
following functional blocks:
VPP Switch Input TTL-CMOS Converters
The VPP inputs are designed to accommodate a wide
range of 3V and 5V logic families. The input threshold
voltage is 1.4V with ≈ 100mV of hysteresis. The inputs
enable the bias generator, the gate charge pumps and the
protection circuitry. When the inputs are turned off, the
entire circuit is powered down and the VDD and VPPIN
supply currents drop below 1µA.
VPP Break-Before-Make Switch Control
The VPP input section has built-in delays to ensure that the
VPP switchs are non-overlapping. Further, the gate charge
pumps include circuitry which ramps the NMOS switches
on slowly but turns them off quickly.
VPP Bias, Oscillator and Gate Charge Pump
When either the VPPIN-VPPOUT or VCC(IN)-VPPOUT switch
is enabled, a bias current generator and high frequency
oscillator are turned on. An on-chip capacitive charge
pump generates approximately 23V of gate drive for the
internal low RDS(ON) NMOS VPPIN-VPPOUT switch from
the VPPIN power supply. The gate of the VCC(IN)-VPPOUT
NMOS switch is either powered by the external 12V
regulator (if left on) or automatically from a built-in charge
pump powered from the VDD supply when the external 12V
supply drops below 10V. The VDD supply current drops
below 1µA when switched to either the 0V or Hi-Z mode.
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