LT3510_12 Datasheet, PDF (8/30 Pages) Linear Technology – Monolithic Dual Tracking 2A Step-Down Switching

LT3510
PIN FUNCTIONS
V_IN1 (Pin 1): The V_IN1 pin powers the internal control
circuitry for both channels and is monitored by the
undervoltage lockout comparator. The V_IN1 pin is also
connected to the collector of channel 1’s on-chip power
NPN switch. The V_IN1 pin has high dI/dt edges and must
be decoupled to ground close to the pin of the device.
SW1/SW2 (Pins 2, 9): The SW pin is the emitter of the on-
chip power NPN. At switch off, the inductor will drive this
pin below ground with a high dV/dt. An external Schottky
catch diode to ground, close to the SW pin and respective
V_IN decoupling capacitor’s ground, must be used to prevent
this pin from excessive negative voltages.
IND1/IND2 (Pins 3, 8): The IND pin is the input to the
on-chip sense resistor that measures current flowing in
the inductor. When the current in the resistor exceeds
the current dictated by the V_C pin, the SW latch is held in
reset, disabling the output switch. Bias current flows out
of the IND pin when IND is less than 1.6V.
V_OUT1/V_OUT2 (Pins 4, 7): The V_OUT pin is the output to
the on-chip sense resistor that measures current flowing
in the inductor. When the current in the resistor exceeds
the current dictated by the V_C pin, the SW latch is held in
reset, disabling the output switch. Bias current flows out
of the V_OUT pin when V_OUT is less than 1.6V.
PG1/PG2 (Pins 5, 6): The power good pin is an open-col-
lector output that sinks current when the feedback falls
below 90% of its nominal regulating voltage. For V_IN1
above 1V, its output state remains true, although during
shutdown, V_IN1 undervoltage lockout or thermal shutdown,
its current sink capability is reduced. The PG pins can be
left open circuit or tied together to form a single power
good signal.
V_IN2 (Pin 10): The V_IN2 pin is the collector of channel 2’s
on-chip power NPN switch. This pin is independent of V_IN1
and may be connected to the same or a separate supply. In
either case, high dI/dt edges are present and decoupling
to ground must be used close to this pin.
SS1/SS2 (Pins 19, 12): The SS1/2 pins control the soft-
start and sequence of their respective outputs. A single
capacitor from the SS pin to ground determines the outpt
ramp rate. For soft-start and output tracking/sequencing
details, see the Applications Information section.
V_C1/V_C2 (Pins 18, 13): The V_C pin is the output of the
error amplifier and the input to the peak switch current
comparator. It is normally used for frequency compensa-
tion, but can also be used as a current clamp or control
loop override. If the error amplifier drives V_C above the
maximum switch current level, a voltage clamp activates.
This indicates that the output is overloaded and current is
pulled from the SS pin, reducing the regulation point.
FB1/FB2 (Pins 17, 14): The FB pin is the negative input
to the error amplifier. The output switches regulate this
pin to 0.8V, with respect to the exposed ground pad. Bias
current flows out of the FB pin.
SHDN (Pin 15): The shutdown pin is used to turn off both
channels and control circuitry to reduce quiescent current
to a typical value of 9μA. The accurate 1.28V threshold and
input current hysteresis can be used as an undervoltage
lockout, preventing the regulator from operating until the
input voltage has reached a predetermined level. Force
the SHDN pin above its threshold or let it float for normal
operation.
R_T/SYNC (Pin 16): This R_T/SYNC pin provides two modes
of setting the constant switch frequency.
Connecting a resistor from the R_T/SYNC pin to ground
will set the R_T/SYNC pin to a typical value of 0.975V. The
resultant switching frequency will be set by the resistor
value. The minimum value of 15.4k and maximum value of
133k sets the switching frequency to 1.5MHz and 250kHz
respectively.
Driving the R_T/SYNC pin with an external clock signal will
synchronize the switch to the applied frequency. Synchro-
nization occurs on the rising edge of the clock signal after
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