LTM4675_15 Datasheet, PDF (78/128 Pages) Linear Technology – Dual 9A or Single 18A Module Regulator with Digital Power System Management

LTM4675
APPENDIX B
PMBUS SERIAL DIGITAL INTERFACE
The LTM4675 communicates with a host (master) using the
standard PMBus serial bus interface. The Timing Diagram,
Figure 36, shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The LTM4675 is a slave device. The master can com-
municate with the LTM4675 using the following formats:
n _{Master transmitter, slave receiver}
n _{Master receiver, slave transmitter}
The following PMBus protocols are supported:
n _{Write Byte, Write Word, Send Byte, Block Write}
n _{Read Byte, Read Word, Block Read}
n _{Block Write -- Block Read Process Call}
n _{Alert Response Address}
Figure 38 to Figure 54 illustrate the aforementioned PMBus
protocols. All transactions support PEC (parity error check)
and GCP (group command protocol). The Block Read
supports 255 bytes of returned data. For this reason, the
PMBus timeout may be extended when reading the fault log.
Figure 37 is a key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in the following figures is a
mandatory value for that field.
The data formats implemented by PMBus are:
n _{Master transmitter transmits to slave receiver. The}
transfer direction in this case is not changed.
n _{Master reads slave immediately after the first byte. At}
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes a
master receiver and the slave receiver becomes a slave
transmitter.
n _{Combined format. During a change of direction within}
a transfer, the master repeats both a start condition
and the slave address but with the R/W bit reversed.
In this case, the master receiver terminates the transfer
by generating a NACK on the last byte of the transfer
and a STOP condition.
SDA
t_f
t_LOW
SCL
t_HD(STA)
START
CONDITION
t_r
t_SU(DAT)
t_f
t_HD(SDA)
t_HD(DAT)
t_HIGH
t_SU(STA)
REPEATED START
CONDITION
Figure 36. Timing Diagram
t_SP
t_r
t_BUF
t_SU(STO)
STOP
CONDITION
4675 F36
START
CONDITION
4675f
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