LTC2926 Datasheet, PDF (7/28 Pages) Linear Technology – MOSFET-Controlled Power Supply Tracker

LTC2926
PI FU CTIO S _{GN/UFD Packages}
D1, S1, D2, S2 (Pins 6, 4, 15, 17/Pins 4, 2, 13, 15):
Remote Sense Switches #1 and #2. A 10Ω (max) switch
connects each pair of pins (D1/S1 and D2/S2) after MGATE,
SGATE1 and SGATE2 are all fully enhanced (MGATE >
RAMP + 4.9V or RAMP > V_CC, and SGATE1, SGATE2 >
V_CC + 4.9V). The switch can be used to compensate for
the voltage drop across the external MOSFET that controls
a slave or the master supply. Connect the switch between
the load and the supply’s sense node. Before the external
MOSFET is fully enhanced, a resistor between the supply’s
output and sense nodes provides local feedback. When
the ON pin voltage is low, the switch will open before the
MGATE, SGATE1 and SGATE2 pins will ramp down. Leave
unused switch terminal pairs unconnected.
Exposed Pad (Pin 21, UFD Package Only): Exposed pad
may be left open or connected to device GND.
FAULT (Pin 9/Pin 7): Negative-Logic Fault Input/Output.
Under normal conditions the internal fault latch is not set
and an 8.5µA current pulls up FAULT to a diode drop below
V_CC. When the voltage at FAULT is pulled below 0.5V, a
fault condition is latched and an internal N-channel MOS-
FET pulls FAULT to GND until the latch is reset. The fault
condition also pulls STATUS/PGI low, opens the remote
sense switches, and pulls MGATE, SGATE1 and SGATE2
to GND to disconnect the master and slave supplies from
their loads. Pulling STATUS/PGI below 1V after the power
good time-out delay also latches a fault. The fault latch is
reset when the ON pin voltage is below 0.5V, or when V_CC
is undervoltage. The fault latch is armed when the ON pin
voltage exceeds 0.6V. To auto-retry after a fault, connect
FAULT to the ON pin. Leave the FAULT pin unconnected
if it is unused.
FB1, FB2 (Pins 3, 18/Pins 1, 16): Feedback Control In-
put/Outputs. Each FB pin connects to the feedback node
of a slave supply. Connect an FB pin to the tap point of a
resistive voltage divider between the source (load side)
of the external MOSFET and GND. For a slave supply with
an accessible feedback path, no external MOSFET may
be necessary. In that case, connect an FB pin to the tap
point of a resistive voltage divider between the supply
generator’s feedback node and GND. To prevent damage
to the slave supply, the FB pins will not force the slave’s
feedback node above 2.4V. In addition, it will not actively
sink current even when the LTC2926 is not powered. Tie
unused FB pins to GND.
GND (Pin 10/Pin 8): Device Ground.
MGATE (Pin 12/Pin 10): Master Gate Drive for External
N-Channel MOSFET/Master Ramp. When the ON pin is
high, an internal 10µA current charges the gate of an
external N-channel MOSFET. A capacitor from MGATE
to GND sets the master ramp rate. Add a 10Ω resistor
between the capacitor and the MOSFET’s gate to prevent
high frequency oscillations. An internal charge pump
guarantees that the MGATE pin voltage will pull up to
5.5V above V_CC, which ensures that logic-level N-channel
MOSFETs are fully enhanced. When the ON pin is pulled
low, the MGATE pin is pulled to GND by a 10µA current
source. Upon a fault condition, the MGATE pin is pulled
low immediately with 20mA. To create a master ramp
signal without an external MOSFET, tie the MGATE pin to
the RAMP pin. A weak internal clamp on the RAMP pin
limits MGATE to V_CC + 1V in this case. Leave the MGATE
pin unconnected if it is unused.
ON (Pin 7/Pin 5): On Control Input. The ON pin has
a threshold of 1.23V with 75mV of hysteresis. A high
causes 10µA to flow out of the MGATE pin, ramping up
the supplies. A low causes 10µA to flow into the MGATE
pin, ramping down the supplies. Pull the ON pin below
0.5V to reset the fault latch. Pull the ON pin above 0.6V
after a fault latch reset to arm the fault latch.
PGTMR (Pin 8/Pin 6): Power Good Timer. Connect an
external capacitor between PGTMR and GND to set the
Power Good Time-Out Delay. When the ON pin is above
1.23V, a 10µA current pulls up PGTMR to V_CC, otherwise
an internal N-channel MOSFET pulls PGTMR to GND. If
the voltage on PGTMR exceeds 1.23V and the voltage
on STATUS/PGI is not above 1.23V, a fault condition is
latched, the remote sense switches are opened, and FAULT,
STATUS/PGI, MGATE, SGATE1, SGATE2 and RSGATE will
be immediately pulled to GND. To disable the Power Good
Timer tie PGTMR to GND.
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