LTC2268-12 Datasheet, PDF (7/32 Pages) Linear Technology – 12-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs

LTC2268-12/
LTC2267-12/LTC2266-12
TIMING DIAGRAMS
2-Lane Output Mode, 16-Bit Serialization
ANALOG
INPUT
ENC^–
ENC⁺
DCO^–
t_AP
N
t_ENCH
t_ENCL
N+1
t_SER
DCO⁺
FR^–
t_FRAME
t_DATA
t_SER
FR⁺
OUT#A^–
OUT#A⁺
OUT#B^–
OUT#B⁺
t_PD
t_SER
D3 D1 D_X* 0 D11 D9 D7 D5 D3 D1 D_X* 0 D11 D9 D7
D2 D0 D_Y* 0 D10 D8 D6 D4 D2 D0 D_Y* 0 D10 D8 D6
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
226812 TD01
*D_X AND D_Y ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D_X AND D_Y ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
2-Lane Output Mode, 14-Bit Serialization
ANALOG
INPUT
ENC^–
ENC⁺
DCO^–
t_AP
N
t_ENCH
t_ENCL
N+1
t_SER
DCO⁺
FR^–
t_FRAME
t_DATA
t_SER
FR⁺
OUT#A^–
OUT#A⁺
OUT#B^–
OUT#B⁺
t_PD
t_SER
D5 D3 D1 D_X* D11 D9 D7 D5 D3 D1 D_X* D11 D9 D7 D5
D4 D2 D0 D_Y* D10 D8 D6 D4 D2 D0 D_Y* D10 D8 D6 D4
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
NOTE THAT IN THIS MODE, FR⁺/FR^– HAS TWO TIMES THE PERIOD OF ENC⁺/ENC^–
*D_X AND D_Y ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D_X AND D_Y ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
N+2
D3 D1
D2 D0
D_X* D11 D9 D7
D_Y* D10 D8 D6
SAMPLE N-3
226812 TD02
22687612f
7