LTC2265-12_15 Datasheet, PDF (7/34 Pages) Linear Technology – 12-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs

LTC2265-12/
LTC2264-12/LTC2263-12
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (R_TERM = 100Ω Differential, C_L = 2pF to GND on Each Output)
t_SER
Serial Data Bit Period
t_FRAME
t_DATA
t_PD
FR to DCO Delay
DATA to DCO Delay
Propagation Delay
Two Lanes, 16-Bit Serialization
Two Lanes, 14-Bit Serialization
Two Lanes, 12-Bit Serialization
One Lane, 16-Bit Serialization
One Lane, 14-Bit Serialization
One Lane, 12-Bit Serialization
(Note 8)
(Note 8)
(Note 8)
1 / (8 • f_S)
s
1 / (7 • f_S)
1 / (6 • f_S)
1 / (16 • f_S)
1 / (14 • f_S)
1 / (12 • f_S)
l 0.35 • t_SER
0.5 • t_SER
0.65 • t_SER
s
l 0.35 • t_SER
0.5 • t_SER
0.65 • t_SER
s
l 0.7n + 2 • t_SER 1.1n + 2 • t_SER 1.5n + 2 • t_SER
s
t_R
Output Rise Time
Data, DCO, FR, 20% to 80%
0.17
ns
t_F
Output Fall Time
Data, DCO, FR, FR, 20% to 80%
DCO Cycle-to-Cycle Jitter t_SER = 1ns
Pipeline Latency
0.17
ns
60
ps_P-P
6
Cycles
SPI Port Timing (Note 8)
t_SCK
SCK Period
Write Mode
l
40
ns
Readback Mode, C_SDO = 20pF, R_PULLUP = 2k
l
250
ns
t_S
CS to SCK Set-Up Time
l
5
ns
t_H
SCK to CS Set-Up Time
l
5
t_DS
SDI Set-Up Time
l
5
t_DH
SDI Hold Time
l
5
t_DO
SCK Falling to SDO Valid Readback Mode, C_SDO = 20pF, R_PULLUP = 2k
l
ns
ns
ns
125
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V_DD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V_DD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V_DD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: V_DD = OV_DD = 1.8V, f_SAMPLE = 65MHz (LTC2265), 40MHz
(LTC2264), or 25MHz (LTC2263), 2-lane output mode, differential ENC⁺/
ENC^– = 2V_P-P sine wave, input range = 2V_P-P with differential drive, unless
otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: V_DD = OV_DD = 1.8V, f_SAMPLE = 65MHz (LTC2265), 40MHz
(LTC2264), or 25MHz (LTC2263), 2-lane output mode, ENC⁺ = single-
ended 1.8V square wave, ENC^– = 0V, input range = 2V_P-P with differential
drive, unless otherwise noted. The supply current and power dissipation
specifications are totals for the entire chip, not per channel.
Note 10: Recommended operating conditions.
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
data rate is 1000Mbps, so t_SER must be greater than or equal to 1ns.
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