LTC2259-12_15 Datasheet, PDF (7/34 Pages) Linear Technology – 12-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs

LTC2261-12
LTC2260-12/LTC2259-12
timing characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (LVDS Mode)
t_D
ENC to Data Delay
t_C
ENC to CLKOUT Delay
C_L = 5pF (Note 8)
C_L = 5pF (Note 8)
l
1.1
1.8
3.2
ns
l
1
1.5
2.7
ns
t_SKEW
DATA to CLKOUT Skew
t_D – t_C (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
5.5
Cycles
SPI Port Timing (Note 8)
t_SCK
SCK Period
Write Mode
l
40
ns
Readback Mode, C_SDO = 20pF, R_PULLUP = 2k l
250
ns
t_S
CS to SCK Setup Time
l
5
ns
t_H
SCK to CS Setup Time
l
5
ns
t_DS
SDI Setup Time
l
5
ns
t_DH
SDI Hold Time
t_DO
SCK Falling to SDO Valid
l
5
Readback Mode, C_SDO = 20pF, R_PULLUP = 2k l
ns
125
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V_DD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V_DD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V_DD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: V_DD = OV_DD = 1.8V, f_SAMPLE = 125MHz (LTC2261),
105MHz (LTC2260), or 80MHz (LTC2259), LVDS outputs with internal
termination disabled, differential ENC⁺/ENC^– = 2V_P-P sine wave, input
range = 2V_P-P with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: V_DD = 1.8V, f_SAMPLE = 125MHz (LTC2261), 105MHz (LTC2260),
or 80MHz (LTC2259), ENC⁺ = single-ended 1.8V square wave, ENC^– = 0V,
input range = 2V_P-P with differential drive, 5pF load on each digital output
unless otherwise noted.
Note 10: Recommended operating conditions.
Timing Diagrams
Full-Rate CMOS Output Mode Timing
All Outputs Are Single Ended and Have CMOS Levels
ANALOG
INPUT
ENC^–
ENC⁺
D0-D11, OF
CLKOUT⁺
CLKOUT ^–
t_AP
N
t_H
N+1
t_L
N+2
N+3
N+4
t_D
N–5
t_C
N–4
N–3
N–2
N–1
226112 TD01
For more information www.linear.com/LTC2261-12
226112fc
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