LTC1650 Datasheet, PDF (7/12 Pages) Linear Technology – Low Glitch 16-Bit Voltage Output DAC

LTC1650
PIN FUNCTIONS
CLK (Pin 7): The TTL Level Input for the Serial Interface
Clock.
CS/LD (Pin 8): The TTL Level Input for the Serial Interface
Enable and Load Control. When CS/LD is low, the CLK
signal is enabled so the data can be clocked in. When
CS/LD is pulled high, data is loaded from the shift register
into the DAC register, updating the DAC output.
CLR (Pin 9): The DAC is cleared to V_RST when this pin is
pulled low. It should be logic high for normal operation.
RSTOUT (Pin 10): The logic output pin that goes active
when any of the supplies drop below 2.5V. This pin is
active low.
REFHI (Pin 11): The Reference Input Pin. The DAC is
capable of 4-quadrant multiplying; this pin can swing
from 4.5V to – 4V.
REFLO F/REFLO S (Pins 12, 13): The Force and Sense Pin
for the Lower Reference Input. This should nominally be
tied to ground. This pin can swing from – 1V to 1V.
AV_SS (Pin 14): The Analog Negative Supply Input. – 5.25V
≤ AV_SS ≤ – 4.75V. Requires a bypass capacitor to ground.
AV_DD (Pin 15): The Analog Positive Supply Input. 4.75V
≤ AV_DD ≤ 5.25V. Requires a bypass capacitor to ground.
UNI/BIP (Pin 16): The Unipolar/Bipolar Selection Pin. For
unipolar operation, tie this pin to V_OUT and for bipolar
operation, tie this pin the REFHI.
WU
W
TI I G DIAGRA
t₂
t₁
t₄
CLK
t₆
t₃
t₇
D_IN
CS/LD
B15
MSB
B14 B13
t₉
t₈
D_OUT
B15
B14
B13
(PREVIOUS
WORD)
B1
B0
LSB
t₅
B1
B0
1650 TD
7