LTC1429 Datasheet, PDF (7/12 Pages) Linear Technology – Clock-Synchronized Switched Capacitor Regulated Voltage Inverter

LTC1429
APPLICATIONS INFORMATION
stacks the flying caps on top of each other and connects the
top of the stack to ground; this forces the bottom of the
stack to a negative voltage. The charge on the flying
capacitors is transferred to the output bypass cap, leaving
it charged to the negative output voltage. This process is
driven by the external 700kHz clock via the SYNC/SD pin.
Figure 4 shows the charge pump configured in tripler
mode. With the external input clock low, C1 and C2 are
charged to V_CC by S1, S3, S5 and S7. At the next rising
clock edge, S1, S3, S5 and S7 open and S2, S4 and S6
close, stacking C1 and C2 on top of each other. S2
connects C1⁺ to ground, S4 connects C1^– to C2⁺ and C2^–
is connected to the output by S6. The charge in C1 and C2
is transferred to C_OUT, setting it to a negative voltage.
Doubler mode works the same way except that the single
flying capacitor (C1) is connected between C1⁺ and C2^–.
S3, S4 and S5 don’t do anything useful in doubler mode.
C1 is charged initially by S1 and S7, and connected to the
output by S2 and S6.
The output voltage is monitored by COMP1, which com-
pares a divided replica of the output at ADJ (COMP for fixed
output parts) to the internal reference. At the beginning of
a cycle, the clock is low, forcing the output of the AND gate
low and charging the flying caps. The next rising clock
edge sets the RS latch, setting the charge pump to transfer
charge from the flying caps to the output capacitor. As
long as the output is below the set point, COMP1 stays low,
the latch stays set and the charge pump runs at the duty
cycle of the input clock signal, gated through the AND gate.
As the output approaches the set voltage, COMP1 will trip
whenever the divided signal exceeds the internal 1.24V
reference, relative to OUT. This resets the RS latch and
truncates the clock pulses, internally reducing the amount
of charge transferred to the output capacitor and regulat-
ing the output voltage. If the output exceeds the set point,
COMP1 stays high, inhibiting the RS latch and disabling
the charge pump.
COMP2 also monitors the divided signal at ADJ, but it is
connected to a 1.18V reference, 5% below the main reference
voltage. When the divided output exceeds this lower refer-
ence voltage, indicating that the output is within 5% of the set
value, COMP2 goes high, turning on the REG output transis-
tor. This is an open drain N-channel device capable of sinking
8mA with a 3.3V V_CC and 15mA with a 5V V_CC. When in “off”
state (divided output more than 5% below V_REF) the drain can
be pulled above V_CC without damage, up to a maximum of
12V above ground. Note that the REG output only indicates
if the magnitude of the output is below the magnitude of the
set point by 5% (i.e., V_OUT > –4.75V for a – 5V set point). If
the magnitude of the output is forced higher than the magni-
tude of the set point (i.e., to – 6V when the output is set for
– 5V) the REG output will stay low.
OUTPUT RIPPLE
Output ripple in the LTC1429 comes from two sources:
voltage droop at the output capacitor between clocks and
frequency response of the regulation loop. Voltage droop
is easy to calculate. With a typical external input clock
frequency of 700kHz, the charge on the output capacitor
is refreshed once every 1.43µs. With a 15mA load and a
3.3µF output capacitor, the output will droop by:
) ) ^{ILOAD ×}
∆t
C_OUT
= 15mA ×
1.43µs
3.3µF
= 6.5mV
There can be a significant ripple component when the
output is heavily loaded, especially if the output capacitor
is small or the external input clock frequency is low. If
absolute minimum output ripple is required, a 10µF or
greater output capacitor, high input clock rate (F_SYNC) and
lower value (< 0.1µF) of flying capacitor should be used.
Regulation loop frequency response is the other major
contributor to output ripple. The LTC1429 regulates the
output voltage by limiting the amount of charge trans-
ferred to the output capacitor on a cycle-by-cycle basis.
The output voltage is sensed at the ADJ pin (COMP for
fixed output versions) through an internal or external
resistor divider from the OUT pin to ground. As the flying
caps are first connected to the output, the output voltage
begins to change quite rapidly. As soon as it exceeds the
set point, COMP1 trips, switching the state of the charge
pump and stopping the charge transfer. Because the RC
time constant of the capacitors and the switches is quite
short, the ADJ pin must have a wide AC bandwidth to be
able to respond to the output in time. External parasitic
capacitance at the ADJ pin can reduce the bandwidth to the
point where the comparator cannot respond by the time
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