LTC1401 Datasheet, PDF (7/20 Pages) Linear Technology – Complete SO-8, 12-Bit, 200ksps ADC with Shutdown

LTC1401
APPLICATIONS INFORMATION
Conversion Details
The LTC1401 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit serial output based on a precision
internal reference. The control logic provides an easy
interface to microprocessors and DSPs through serial
3-wire connections.
A rising edge on the CONV input starts a conversion. At the
start of a conversion the successive approximation regis-
ter (SAR) is reset. Once a conversion cycle has begun, it
cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A_IN input connects to the sample-and-hold
capacitor during the acquire phase and the comparator
offset is nulled by the feedback switch. In this acquire
phase, it typically takes 315ns for the sample-and-hold
capacitor to acquire the analog signal. During the convert
phase, the comparator feedback switch opens, putting the
comparator into the compare mode. The input switches
C_SAMPLE to ground, injecting the analog input charge onto
the summing junction. This input charge is successively
compared with the binary-weighted charges supplied by
the capacitive DAC. Bit decisions are made by the high
speed comparator. At the end of a conversion, the DAC
SAMPLE
A_IN
C_SAMPLE
HOLD
DAC
C_DAC
V_DAC
SAMPLE
S1
–
COMP
+
S
A
R
D_OUT
LTC1401 • F01
Figure 1. A_IN Input
output balances the A_IN input charge. The SAR contents (a
12-bit data word) which represent the input voltage, are
presented through the serial pin D_OUT.
Dynamic Performance
The LTC1401 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2a shows a
typical LTC1401 FFT plot.
0
–10
–20
f_SAMPLE = 200kHz
f_IN = 49.853516kHz
SINAD = 68.5dB
–30 ^{THD = –72.4dB}
–40
V_CC = 3V
T_A = 25°C
–50
– 60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
LTC1401 • F02a
Figure 2a. LTC1401 Nonaveraged, 4096 Point FFT
Plot with 50kHz Input Frequency
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from DC to half the sampling frequency.
Figure 2a shows a typical spectral content with a 200kHz
sampling rate and a 50kHz input. The dynamic perfor-
mance is excellent for input frequencies up to the Nyquist
limit of 100kHz as shown in Figure 2b.
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