LTC1143_15 Datasheet, PDF (7/20 Pages) Linear Technology – Dual High Efficiency SO-16 Step-Down Switching Regulator Controllers

LTC1143/LTC1143L
LTC1143L-ADJ
W
FUNCTIONAL DIAGRA
Only one regulator block shown. Connections shown for LT1143/LTC1143L; changes create LTC1143L-ADJ
13(5) V_IN
4(12) P-DRIVE
SENSE⁺
1(9)
SENSE^–
16(8)
3(11) GROUND
SLEEP
V
S
V_TH2
14(6)
C_T
R
Q
S
V_{TH1 –}
T
+
OFF-TIME
CONTROL
V_IN
SENSE^–
C
25mV TO 150mV
–+
I_TH
13k
15(7)
SHUTDOWN
(LTC1143/LTC1143L)
2(10)
V_FB
(LTC1143L-ADJ)
V_OS
G
1.25V
X REFERENCE
5pF
X
100k
1143 FD
U
OPERATION Refer to Functional Diagram and Figure 1.
The LTC1143 series consists of two individual regulator
blocks, each using current mode, constant off-time archi-
tectures to switch an external power MOSFET. The two
LTC1143/LTC1143L regulators are internally set for 3.3V
and 5V, while the two LTC1143L-ADJ regulators have
externally programmable output voltages. Operating fre-
quency is individually set on each section by external
capacitors at the timing capacitor Pins 6 and 14.
The output voltage is sensed by voltage comparator V and
gain block G, which compare the divided output voltage
with a reference voltage of 1.25V. To optimize efficiency,
the LTC1143 series automatically switches between two
modes of operation, burst and continuous. The voltage
comparator is the primary control element when the
device is in Burst Mode operation, while the gain block
controls the output voltage in continuous mode.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 1 (9) and
16 (8) connected across an external shunt in series with
the inductor. When the voltage across the shunt reaches
its threshold value, the P-drive output is switched to V_IN,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 14 (6) is now allowed to discharge at a
rate determined by the off-time controller. The discharge
current is made proportional to the feedback voltage to
model the inductor current, which decays at a rate that is
also proportional to the output voltage.
When the voltage on the timing capacitor has discharged
past V_TH1, comparator T trips, setting the flip-flop. This
causes the P-drive output to go low, turning the P-channel
MOSFET back on. The cycle then repeats.
As the load current increases, the output voltage
decreases slightly. This causes the output of the gain
stage [Pin 15 (7)] to increase the current comparator
threshold, thus tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel
MOSFET is held off by comparator V and the timing
capacitor continues to discharge below V_TH1. When the
timing capacitor discharges past V_TH2, voltage compara-
tor S trips, causing the internal sleep line to go low.
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