LTC1065_09 Datasheet, PDF (7/16 Pages) Linear Technology – DC Accurate, Clock-Tunable Linear Phase 5th Order Bessel Lowpass Filter

LTC1065
PI FU CTIO S
Input Pin (Pin 1, N Package)
Pin 1 is the filter input and it is connected to an internal
switched-capacitor resistor. If the input pin is left floating,
the filter output will saturate. The DC input impedance of
pin 1 is very high; with ±5V supplies and 1MHz clock, the
DC input impedance is typically 1GΩ. A resistor R_IN in
series with the input pin will not alter the value of the filter’s
DC output offset (Figure 1). R_IN should however, be limited
to a maximum value (Table 1), otherwise the filter’s pass-
band will be affected. Refer to the Applications Information
section for more details.
V_IN
R_{IN 1}
8
2
V^{– 3}
LTC1065
7
V_OUT
6 _V+
4
5 _fCLK
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Figure 1.
Table 1. R_IN(MAX) vs Clock and Power Supply
f_CLK = 4MHz
f_CLK = 3MHz
f_CLK = 2MHz
f_CLK = 1MHz
f_CLK = 500kHz
f_CLK = 100kHz
V_S = ±7.5V
1.82k
3.01k
4.32k
9.09k
17.8k
95.3k
R_IN(MAX)
V_S = ±5V
–
2.49k
3.65k
8.25k
16.9k
90.9k
V_S = ±2.5V
–
–
2.37k
7.5k
16.9k
90.9k
Output Pin (Pin 7, N Package)
Pin 7 is the filter output. This pin can typically source over
20mA and sink 2mA. Pin 7 should not drive long coax
cables, otherwise the filter’s total harmonic distortion will
degrade. The maximum load the filter output can drive and
still maintain the distortion levels, shown in the Typical
Performance Characteristics, is 20k.
Clock Input Pin (Pin 5, N Package)
An external clock, when applied to pin 5, tunes the filter
cutoff frequency. The clock-to-cutoff frequency ratio is
100:1. The high (V_HIGH) and low (V_LOW) clock logic
threshold levels are illustrated in Table 2. Square wave
clocks with duty cycles between 30% and 50% are strongly
recommended. Sinewave clocks are not recommended.
Table 2. Clock Pin Threshold Levels
POWER SUPPLY
V_S = ±2.5V
V_S = ±5V
V_S = ±7.5V
V_S = ±8V
V_S = 5V, 0V
V_S = 12V, 0V
V_S =15V, 0V
V_HIGH
1.5V
3V
4.5V
4.8V
4V
9.6V
12V
V_LOW
0.5V
1V
1.5V
1.6V
3V
7.2V
9V
Clock Output Pin (Pin 4, N Package)
Any external clock applied to the clock input pin appears
at the clock output pin. The duty cycle of the clock output
equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
supply rails. When the LTC1065 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
clock output pin with a 30% duty cycle. The clock output
pin can be used to drive other LTC1065s or other ICs. The
maximum capacitance, C_L(MAX), the clock output pin can
drive is illustrated in Figure 2.
200
180 V_S = ±2.5V
160
T_A = 25°C
140
120
100 ^VS ^{= ±5V}
80 V_S = ±7.5V
60
40
20
0
1
2
3 4 5 6 7 8 9 10
CLOCK FREQUENCY (MHz)
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Figure 2. Maximum Load Capacitance at the Clock Output Pin
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