LT1910 Datasheet, PDF (7/12 Pages) Linear Technology – Protected High Side MOSFET Driver

U
OPERATIO
OFF NORMAL
IN
0V
V^{+ 12V}
GATE
OVERCURRENT
0V
3.5V
2.9V
TIMER
0V
5V
FAULT
0V
Figure 1. Timing Diagram
NORMAL
3.4V
1910 F01
LT1910
APPLICATIO S I FOR ATIO
Input/Supply Sequencing
There are no input/supply sequencing requirements for
the LT1910. The IN pin may be taken up to 15V with the
supply at 0V. When the supply is turned on with the IN pin
set HIGH, the MOSFET turn-on will be inhibited until the
timing capacitor charges up to 2.9V (i.e., for one restart
cycle).
Isolating the Inputs
Operation in harsh environments may require isolation to
prevent ground transients from damaging control logic.
The LT1910 easily interfaces to low cost optoisolators.
The network shown in Figure 2 ensures that the input will
be pulled above 2V, but not exceed the absolute maximum
rating for supply voltages of 12V to 48V over the entire
LOGIC
INPUT
12V TO 48V
2k
100k
LOGIC GROUND
LT1910
4
IN
51k
GND
1 ^{1910 F02}
POWER GROUND
Figure 2. Isolating the Input
temperature range. The optoisolator must have less than
20µA of dark current (leakage) at hot in order to maintain
the OFF State (see Figure 2).
Drain Sense Configuration
The LT1910 uses supply referenced current sensing. One
input of the current sense comparator is connected to a
drain sense pin, while the second input is offset 65mV below
the supply inside the device. For this reason, Pin 8 of the
LT1910 must be treated not only as a supply pin, but also
as the reference input for the current sense comparator.
Figure 3 shows the proper drain sense configuration for
the LT1910. Note that the SENSE pin goes to the drain end
of the sense resistor, while the V⁺ pin is connected to the
24V
5V
FAULT OUTPUT
INPUT
R1
5.1k
3
LT1910
FAULT
V⁺
8
4
6
IN SENSE
2
5
TIMER GATE
GND
1
C_T
+
1µF
C1
100µF
50V
R_S
0.02Ω
(PTC)
Q1
IRFZ34
24V
2A
SOLENOID
0V
1910 F03
Figure 3. Drain Sense Configuration
sn1910 1910fs
7