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LT1310_15 Datasheet, PDF (7/12 Pages) Linear Technology – 1.5A Boost DC/DC Converter with Phase-Locked Loop
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OPERATIO
CT Selection for Operating Frequency
To synchronize to an external input signal, the timing
capacitor and PLL filter components must be chosen
properly. This is a simple process and can be done using
the graph in Figure␣ 2a.
In Figure 2a, operating frequency is plotted versus timing
capacitor (CT) with the upper and lower lines correspond-
ing to the minimum and maximum lock frequency given a
specific CT value. To choose the right timing capacitor,
find the intersection of the desired operating frequency
and the dashed line. Then move to the corresponding CT
value.
Alternately, use the following equations as a starting point:
for fLOCK ≥ 2MHz:
CT
=

0.75
250 • 10–6
fLOCK
–
40
•
10–12


for fLOCK ≤ 2MHz:
CT
=

0.75
310 • 10–6
fLOCK
–
60
•
10–12


LT1310
Because the lock range for the PLL is nearly 2:1, the
nearest standard value NP0 capacitor can be used. For
the application shown in Figure 1, a 1.6MHz switching
frequency corresponds to an 100pF timing capacitor.
Since the switching frequency affects inductor ripple
current, the inductor must also be scaled. Table 1 shows
recommended component values for various switching
frequencies.
Table 1. Recommended Component Values for Various Switching
Frequencies (RLP = 3.01k)
SWITCHING
FREQUENCY
CT
CC
CLP
RC
L1
600kHz
330pF 1500pF 2700pF 10k
10µH
1MHz
180pF 1000pF 2200pF 10k 6.2µH
1.6MHz
100pF 820pF 1500pF 15k 5.6µH
2MHz
68pF 820pF 1500pF 15k 4.7µH
2.5MHz
47pF 330pF 1500pF 20k 3.3µH
3MHz
33pF 330pF 1000pF 20k 2.7µH
100k
10k
MAXIMUM
LOCK
FREQUECY
1k
MINIMUM
LOCK
FREQUECY
100
10
10k
100k
1M
FREQUENCY (Hz)
10M
1310 F02a
Figure 2a. CT vs Operating Frequency
VIN
5V
SHUTDOWN
SYNC IN
L1
C1
4.7µF
CERAMIC
RLP
CLP
LT1310
VIN
SHDN
SYNC
PLL-LPF
VC
SW
FB
CT
GND
RC
CC
178k
VOUT
12V
20.5k
CT
C2
4.7µF
CERAMIC
1310 F02a
Figure 2b. Circuit Used for CT Selection
sn1310 1310fs
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