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LTM9008-14_15 Datasheet, PDF (6/38 Pages) Linear Technology – 14-Bit, 65Msps/40Msps/ 25Msps Low Power Octal ADCs
◁
LTM9008-14/
LTM9007-14/LTM9006-14
Power Requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
LTM9008-14
LTM9007-14
LTM9006-14
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD
Analog Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
OVDD Output Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
IVDD
Analog Supply Current Sine Wave Input
l
357 400
232 275
175 250 mA
IOVDD
Digital Supply Current 1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode l
2-Lane Mode, 3.5mA Mode l
32
60
50 58
94 104
32
58
48 54
92 102
30
mA
56
mA
48 54 mA
90 100 mA
PDISS Power Dissipation
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode l
2-Lane Mode, 3.5mA Mode l
700
751
733 824
812 907
475
522
504 592
583 679
369
mW
416
mW
401 547 mW
477 630 mW
PSLEEP Sleep Mode Power
2
2
2
mW
PNAP Nap Mode Power
170
170
170
mW
PDIFFCLK Power Decrease With Single-Ended Encode Mode Enabled
40
40
40
mW
(No Decrease for Sleep Mode)
Timing Characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
LTM9008-14
LTM9007-14
LTM9006-14
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS
Sampling Frequency (Notes 10,11)
l5
65 5
40 5
25 MHz
tENCL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
l 7.3 7.69 100 11.88 12.5 100 19 20 100
ns
Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100
ns
tENCH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
l 7.3 7.69 100 11.88 12.5 100 19 20 100
ns
Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
SYMBOL PARAMETER
CONDITIONS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
tFRAME
tDATA
tPD
FR to DCO Delay
DATA to DCO Delay
Propagation Delay
(Note 8)
(Note 8)
(Note 8)
tR
Output Rise Time
Data, DCO, FR, 20% to 80%
tF
Output Fall Time
DCO Cycle-Cycle Jitter
Pipeline Latency
Data, DCO, FR, 20% to 80%
tSER = 1ns
MIN
TYP
MAX
UNITS
1/(8 • fS)
1/(7 • fS)
1/(6 • fS)
1/(16 • fS)
1/(14 • fS)
1/(12 • fS)
l 0.35 • tSER
0.5 • tSER
0.65 • tSER
l 0.35 • tSER
0.5 • tSER
0.65 • tSER
l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER
0.17
0.17
60
6
s
s
s
s
s
s
s
s
s
ns
ns
psP-P
Cycles
6
For more information www.linear.com/LTM9008-14
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