LTC3900_1 Datasheet, PDF (6/20 Pages) Linear Technology – Synchronous Rectifier Driver for Forward Converters

LTC3900
Pin Functions
CS⁺, CS^– (Pin 1, 2): Current Sense Differential Input.
Connect CS⁺ through a series resistor to the drain of the
external catch MOSFET, Q4. Connect CS^– to the source.
The LTC3900 monitors the CS inputs 250ns after CG goes
high. If the inductor current reverses and flows into the
MOSFET causing CS⁺ to rise above CS^– by more than
10.5mV, the LTC3900 pulls CG low. See the Current Sense
section for more details on choosing the resistance value
for R_CS1 to R_CS3.
CG (Pin 3): Catch MOSFET Gate Driver. This pin drives the
gate of the external N-channel catch MOSFET, Q4.
V_CC (Pin 4): Main Supply Input. This pin powers the driv-
ers and the rest of the internal circuitry. Bypass this pin
to GND using a 4.7µF ceramic capacitor in close proximity
to the LTC3900.
FG (Pin 5): Forward MOSFET Gate Driver. This pin drives
the gate of the external N-channel forward MOSFET, Q3.
GND (Pin 6): The V_CC bypass capacitor should be con-
nected directly to this GND pin.
TIMER (Pin 7): Timer Input. Connect this pin to an external
R-C network to program the timeout period. The LTC3900
resets the timer at every negative transition of the SYNC
input. If the SYNC signal is missing or incorrect, the
LTC3900 pulls both CG and FG low once the TIMER pin
goes above the timeout threshold. See the Timer section
for more details on programming the timeout period.
SYNC (Pin 8): Driver Synchronization Input. This input
is signal edge sensitive. A negative voltage slew at SYNC
forces FG to pull high and CG to pull low. A positive volt-
age slew at SYNC forces FG to pull low and CG to pull
high. The SYNC input can accept both pulse or square
wave signals.
Block Diagram
SYNC 8
CS⁺ 1
CS^– 2
TIMER 7
+1.4V
–1.4V
S⁺
SYNC⁺
S–
SYNC^–
–+
IS
10.5mV
Z_CS
11V
TMR
R1
180k
R2
Z_TMR
45k
0.5 • V_CC
DISABLE
DRIVER
UVLO
SYNC
AND
DRIVER
LOGIC
TIMER
RESET
M_TMR
3900 BD
4 V_CC
5 FG
3 CG
6 GND
3900fb
6