LTC3672B-1_15 Datasheet, PDF (6/12 Pages) Linear Technology – Monolithic Fixed-Output 400mA Buck Regulator with Dual

LTC3672B-1
PIN FUNCTIONS
SW (Pin 1): Switch Node Connection to Inductor. This pin
connects to the drains of the buck regulator’s main PMOS
and synchronous NMOS switches.
GND (Pin 2): Ground.
ENALL (Pin 3): Enables all three outputs when high, shuts
down the IC when low. This is a MOS gate input. An internal
5.5MΩ resistor pulls this pin to ground.
BUCKOUT (Pin 4): Output Voltage Sense Connection for
the Buck Regulator.
V_IN1 (Pin 5): Power Input for the First Low Dropout Linear
Regulator, LDO1. This pin may be connected to the buck
regulator’s output, V_IN, or a voltage not exceeding V_IN.
LDO1 (Pin 6): Output of the First Low Dropout Linear
Regulator. This pin must be bypassed to ground with a
1μF or greater ceramic capacitor.
LDO2 (Pin 7): Output of the Second Low Dropout Linear
Regulator. This pin must be bypassed to ground with a
1μF or greater ceramic capacitor.
V_IN (Pin 8): Input Bias Supply for the IC, and Power
Input for the Buck Regulator and LDO2. This pin should
be bypassed to ground with a 2.2μF or greater ceramic
capacitor.
Exposed Pad (Pin 9): Ground. The Exposed Pad must be
soldered to PCB.
BLOCK DIAGRAM
SW
1
400mA BUCK
GND
2
ENABLE
BUCK
2.25MHz
OSC
ENALL
3
5.5M
LOGIC
800mV
REFERENCE
ENABLE LDO2
ENABLE LDO1
4
8
BUCKOUT V_IN
5
V_IN1
1M
800k
LDO2
LDO1
LDO1
6
LDO2
7
400k
2M
800k
800k
EXPOSED PAD (GND)
9
3672b1 BD
3672B1f
6