LTC2265-14 Datasheet, PDF (6/32 Pages) Linear Technology – 14-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs

LTC2265-14/
LTC2264-14/LTC2263-14
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. (Note 9)
LTC2265-14
LTC2264-14
LTC2263-14
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
V_DD
Analog Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
OV_DD Output Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
I_VDD
Analog Supply Current Sine Wave Input
l
84 98
53 63
42 50
mA
I_OVDD
Digital Supply Current 1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode l
2-Lane Mode, 3.5mA Mode l
11
20
15 18
28 32
10
19
15 17
28 31
10
mA
18
mA
14 17
mA
27 31
mA
P_DISS Power Dissipation
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode l
2-Lane Mode, 3.5mA Mode l
171
187
178 209
202 234
113
130
122 144
146 169
94
mW
108
mW
101 121 mW
124 146 mW
P_SLEEP
P_NAP
Sleep Mode Power
Nap Mode Power
1
1
1
mW
60
60
60
mW
P_DIFFCLK Power Increase with Differential Encode Mode Enabled
20
20
20
mW
(No Increase for Sleep Mode)
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. (Note 5)
LTC2265-14
LTC2264-14
LTC2263-14
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
f_S
Sampling Frequency (Notes 10, 11)
l5
65 5
45 5
25 MHz
t_ENCL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100
ns
Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100
ns
t_ENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100
ns
Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100
ns
t_AP
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
6
22654314f