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LTC2258-14_15 Datasheet, PDF (6/34 Pages) Linear Technology – 14-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs
LTC2258-14
LTC2257-14/LTC2256-14
Power Requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2258-14
LTC2257-14
LTC2256-14
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
OVDD
IVDD
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
DC Input
Sine Wave Input
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
l 1.1
1.9 1.1
1.9 1.1
1.9
V
l
44.7 49.5
45.3
27 30
27.9
19.5 22
mA
19.9
mA
IOVDD
PDISS
Digital Supply Current
Power Dissipation
LVDS Output Mode
Sine Wave Input, OVDD=1.2V
DC Input
l
Sine Wave Input, OVDD=1.2V
2.6
80.5 90
84.7
1.6
48.6 54
52.1
1.1
mA
35.1 40
mW
37.1
mW
VDD
Analog Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
OVDD Output Supply Voltage (Note 10)
l 1.7
1.9 1.7
1.9 1.7
1.9
V
IVDD
Analog Supply Current Sine Wave Input
l
48.9 54
31.4 35
23.5 26
mA
IOVDD Digital Supply Current Sine Input, 1.75mA Mode l
(0VDD = 1.8V)
Sine Input, 3.5mA Mode
l
20.7 23
40.5 44
20.7 23
40.5 44
20.7 23
mA
40.5 44
mA
PDISS Power Dissipation
Sine Input, 1.75mA Mode l
Sine Input, 3.5mA Mode
l
125.3 139
160.9 177
93.8 105
129.4 143
79.6 89
mW
115.2 126 mW
All Output Modes
PSLEEP Sleep Mode Power
0.5
0.5
0.5
mW
PNAP Nap Mode Power
9
9
9
mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
10
10
10
mW
(No increase for Nap or Sleep Modes)
Timing Characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2258-14
LTC2257-14
LTC2256-14
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS
Sampling Frequency (Note 10)
l1
65 1
40 1
25 MHz
tL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500
ns
Duty Cycle Stabilizer On l 2.0 7.69 500 2.00 12.5 500 2.00 20 500
ns
tH
ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500
ns
Duty Cycle Stabilizer On l 2.0 7.69 500 2.00 12.5 500 2.00 20 500
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
SYMBOL PARAMETER
CONDITIONS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
tC
tSKEW
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
CL = 5pF (Note 8)
CL = 5pF (Note 8)
tD – tC (Note 8)
Full Data Rate Mode
Double Data Rate Mode
MIN
TYP
MAX
UNITS
l
1.1
1.7
3.1
ns
l
1
1.4
2.6
ns
l
0
0.3
0.6
ns
5.0
Cycles
5.5
Cycles
225814fc
6
For more information www.linear.com/LTC2258-14