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LTC2215_15 Datasheet, PDF (6/36 Pages) Linear Technology – 16-Bit, 80Msps/65Msps Low Noise ADC
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LTC2216/LTC2215
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)
LTC2215
LTC2216
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX UNITS
VDD
Analog Supply Voltage
PSHDN Shutdown Power
Standard LVDS Output Mode
(Note 8)
SHDN = VDD
l 3.135 3.3 3.465 3.135 3.3 3.465
V
17
17
mW
OVDD
IVDD
Output Supply Voltage
Analog Supply Current
(Note 8)
l 3 3.3 3.6 3 3.3 3.6
V
l
217 290
300 370
mA
IOVDD Output Supply Current
PDIS Power Dissipation
Low Power LVDS Output Mode
l
75 90
75 90
mA
l
964 1254
1240 1518 mW
OVDD Output Supply Voltage
IVDD Analog Supply Current
IOVDD Output Supply Current
PDIS Power Dissipation
CMOS Output Mode
(Note 8)
l 3 3.3 3.6 3 3.3 3.6
V
l
215 290
298 370
mA
l
42 50
42 50
mA
l
848 1122
1120 1386 mW
OVDD Output Supply Voltage
(Note 8)
l 0.5
3.6 0.5
3.6
V
IVDD Analog Supply Current
PDIS Power Dissipation
l
212 290
295 370
mA
l
700 957
970 1220 mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2215
LTC2216
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX UNITS
fS
Sampling Frequency
(Note 8)
l1
65 1
80 MHz
tL
ENC Low Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l 7.31 7.692 500 5.94 6.25 500
ns
l 5 7.692 500 4.06 6.25 500
ns
tH
ENC High Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l 7.31 7.692 500 5.94 6.25 500
ns
l 5 7.692 500 4.06 6.25 500
ns
LVDS Output Mode (Standard and Low Power)
tD
tC
tSKEW
ENC to DATA Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
(Note 7)
(Note 7)
(tC-tD) (Note 7)
l 1.3 2.5 3.8 1.3 2.5 3.8
ns
l 1.3 2.5 3.8 1.3 2.5 3.8
ns
l –0.6 0 0.6 –0.6 0 0.6
ns
tRISE
tFALL
Data Latency
Output Rise Time
Output Fall Time
Data Latency
0.5
0.5
ns
0.5
0.5
ns
7
7
Cycles
CMOS Output Mode
tD
tC
tSKEW
Data Latency
ENC to DATA Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Data Latency
(Note 7)
(Note 7)
(tC-tD) (Note 7)
Full Rate CMOS
Demuxed
l 1.3 2.7
l 1.3 2.7
l –0.6 0
7
7
4 1.3 2.7
4 1.3 2.7
0.6 –0.6 0
7
7
4
ns
4
ns
0.6
ns
Cycles
Cycles
22165f
6
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