LTC2204_15 Datasheet, PDF (6/36 Pages) Linear Technology – 16-Bit, 65Msps/40Msps ADCs

LTC2205/LTC2204
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
LTC2204
LTC2205
MIN TYP MAX MIN TYP MAX UNITS
f_S
Sampling Frequency
l1
40
1
65
MHz
t_L
ENC Low Time
Duty Cycle Stabilizer Off (Note 7)
l 10.4 12.5 500 6.40 7.69 500
ns
Duty Cycle Stabilizer On (Note 7)
l 2.7 12.5 500 2.70 7.69 500
ns
t_H
ENC High Time
Duty Cycle Stabilizer Off (Note 7)
l 10.4 12.5 500 6.40 7.69 500
ns
Duty Cycle Stabilizer On (Note 7)
2.7 12.5 500 2.70 7.69 500
ns
t_AP
Sample-and-Hold
Aperture Delay
0.7
0.7
ns
t_D
t_C
t_SKEW
t_OE
ENC to DATA Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
DATA Access Time
Bus Relinquish Time
(Note 7)
(Note 7)
(t_D – t_C) (Note 7)
CL = 5pf (Note 7)
(Note 7)
l 1.3 2.7 4.0 1.3 2.7 4.0
ns
l 1.3 2.7 4.0 1.3 2.7 4.0
ns
l –0.6
0
0.6 –0.6
0
0.6
ns
l
5
15
l
5
15
5
15
ns
5
15
ns
Pipeline
Latency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V_DD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V_DD without latchup.
Note 4: V_DD = 3.3V, f_SAMPLE = 65MHz (LTC2205), 40MHz (LTC2204)
differential ENC⁺/ENC^– = 2V_P-P sine wave with 1.6V common mode,
7
7
Cycles
input range = 2.25V_P-P with differential drive (PGA = 0), unless otherwise
specified.
Note 5: Integral nonlinearity is defined as the deviation of a code from
a “best fit straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
TIMING DIAGRAM
ANALOG
INPUT
ENC^–
ENC⁺
D0-D15, OF
CLKOUT⁺
CLKOUT ^–
t_AP
N+1
N
t_H
t_L
N+2
N+3
t_D
N–7
t_C
N–6
N–5
N–4
N+4
N–3
22054 TD01
22054fc
6