LTC1261L Datasheet, PDF (6/12 Pages) Linear Technology – Switched Capacitor Regulated Voltage Inverter

LTC1261L
APPLICATIONS INFORMATION
The LTC1261L uses an inverting charge pump to generate
a regulated negative output voltage that is either equal to
or less than the supply voltage. The LTC1261L needs only
three external capacitors and is available in the MSOP and
SO-8 packages
THEORY OF OPERATION
A block diagram of the LTC1261L is shown in Figure 1. The
heart of the LTC1261L is the charge pump core shown in
the dashed box. It generates a negative output voltage by
first charging the flying capacitor (C1) between V_CC and
ground. It then connects the top of the flying capacitor to
ground, forcing the bottom of the flying capacitor to a
negative voltage. The charge on the flying capacitor is
transferred to the output bypass capacitor, leaving it
charged to the negative output voltage. This process is
driven by the internal 650kHz clock.
Figure 1 shows the charge pump configuration. With the
clock low, C1 is charged to V_CC by S1 and S3. At the next
rising clock edge, S1 and S3 are open and S2 and S4
closed. S2 connects C1⁺ to ground, C1^– is connected to
the output by S4. The charge in C1 is transferred to C_OUT,
setting it to a negative voltage.
The output voltage is monitored by COMP1 which com-
pares a divided replica of the output at ADJ (COMP for
fixed output voltage parts) to the internal reference. At the
beginning of a cycle the clock is low, forcing the output of
the AND gate low and charging the flying capacitor. The
next rising clock edge sets the RS latch, setting the charge
pump to transfer charge from the flying capacitor to the
output capacitor. As long as the output is below the set
point, COMP1 stays low, the latch stays set and the charge
pump runs at the full 50% duty cycle of the clock gated
through the AND gate. As the output approaches the set
voltage, COMP1 will trip whenever the divided signal
exceeds the internal 1.23V reference relative to OUT. This
resets the RS latch and truncates the clock pulses, reduc-
ing the amount of charge transferred to the output capaci-
tor and regulating the output voltage. If the output exceeds
the set point, COMP1 stays high, inhibiting the RS latch
and disabling the charge pump.
6
V_CC
CLK
650kHz
S
Q
R
S1
C1⁺
C1
S4
S2
C1^–
S3
COMP1
60mV
V_REF = 1.23V
1.17V
V_OUT
+
COMP2
–
Figure 1. Block Diagram
OUT
R2
C_OUT
R1
INTERNALLY
CONNECTED FOR
FIXED OUTPUT
VOLTAGE PARTS
ADJ (COMP)
REG
1261L F01