LTC3225-1_15 Datasheet, PDF (5/14 Pages) Linear Technology – 150mA Supercapacitor Charger

LTC3225/LTC3225-1
TYPICAL PERFORMANCE CHARACTERISTICS
(T_A = 25°C, C_FLY = 1μF, C_IN = 2.2μF, C_TOP = C_BOT, unless otherwise specified)
Charging Profile with Unequal
Initial Output Capacitor Voltage
(Initial V_TOP = 1V, V_BOT = 1.3V)
SHDN
5V/DIV
I_VIN
300mA/DIV
V_COUT
2V/DIV
Charging Profile with 30%
Mismatch in Output Capacitance
(C_TOP > C_BOT)
SHDN
5V/DIV
I_VIN
300mA/DIV
V_COUT
2V/DIV
Charging Profile with 30%
Mismatch in Output Capacitance
(C_TOP < C_BOT)
SHDN
5V/DIV
I_VIN
300mA/DIV
V_COUT
2V/DIV
V_TOP-V_BOT
500mV/DIV
LTC3225
2 SEC/DIV
V_SEL = V_IN
R_PROG = 12k
C_TOP = C_BOT = 1.1F
C_TOP INITIAL VOLTAGE = 1V
C_BOT INITIAL VOLTAGE = 1.3V
3225 G10
V_TOP-V_BOT
200mV/DIV
LTC3225
5 SEC/DIV
V_SEL = V_IN
R_PROG = 12k
C_TOP = 1.43F
C_BOT = 1.1F
C_TOP INITIAL VOLTAGE = 0V
C_BOT INITIAL VOLTAGE = 0V
3225 G11
V_TOP-V_BOT
200mV/DIV
LTC3225
5 SEC/DIV
V_SEL = V_IN
R_PROG = 12k
C_TOP = 1.1F
C_BOT = 1.43F
C_TOP INITIAL VOLTAGE = 0V
C_BOT INITIAL VOLTAGE = 0V
3225 G12
PIN FUNCTIONS
C⁺ (Pin 1): Flying Capacitor Positive Terminal. A 1μF X5R
or X7R ceramic capacitor should be connected from C⁺
to C^–.
C^– (Pin 2): Flying Capacitor Negative Terminal.
CX (Pin 3): Midpoint of Two Series Supercapacitors. This
pin voltage is monitored and forced to track C_OUT (CX =
C_OUT/2) during charging to achieve voltage balancing of
the top and bottom supercapacitors.
SHDN (Pin 4): Active Low Shutdown Input. A low on SHDN
puts the LTC3225/LTC3225-1 in low current shutdown
mode. Do not float the SHDN pin.
PGOOD (Pin 5): Open-Drain Output Status Indicator. Upon
start-up, this open-drain pin remains low until the output
voltage, V_OUT, is within 6% (typical) of its final value. Once
V_OUT is valid, PGOOD becomes Hi-Z. If V_OUT falls 7.2%
(typical) below its correct regulation level, PGOOD is
pulled low. PGOOD may be pulled up through an external
resistor to an appropriate reference level. This pin is Hi-Z
in shutdown mode.
V_SEL (Pin 6): Output Voltage Selection Input. A logic
low at V_SEL sets the regulated C_OUT to 4.8V (LTC3225)
or 4V (LTC3225-1); a logic high sets the regulated C_OUT
to 5.3V (LTC3225) or 4.5V (LTC3225-1). Do not float the
V_SEL pin.
PROG (Pin 7): Charge Current Programming Pin. A resis-
tor connected between this pin and GND sets the charge
current. (See Applications Information section).
GND (Pin 8, Exposed Pad Pin 11): Charge Pump Ground.
These pins must be soldered directly to PCB ground. The
exposed pad must be soldered to a low impedance PCB
ground for rated thermal performance.
V_IN (Pin 9): Power Supply for the LTC3225/LTC3225-1.
V_IN should be bypassed to GND with a low ESR ceramic
capacitor of more than 2.2μF.
C_OUT (Pin 10): Charge Pump Output Pin. Connect C_OUT to
the top plate of the top supercapacitor. C_OUT provides charge
current to the supercapacitors and regulates the final volt-
age to 4.8V/5.3V (LTC3225) or 4V/4.5V (LTC3225-1).
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