LTC2368-18_15 Datasheet, PDF (5/24 Pages) Linear Technology – 18-Bit, 1Msps, Pseudo- Differential Unipolar SAR ADC with 97dB SNR

LTC2368-18
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
t_SCKL
SCK Low Time
l
4
ns
t_SSDISCK SDI Setup Time From SCK↑
(Note 11)
l
4
ns
t_HSDISCK SDI Hold Time From SCK↑
(Note 11)
l
1
ns
t_SCKCH
SCK Period in Chain Mode
t_SCKCH = t_SSDISCK + t_DSDO (Note 11)
l 13.5
ns
t_DSDO
SDO Data Valid Delay from SCK↑
C_L = 20pF (Note 11)
l
9.5
ns
t_HSDO
SDO Data Remains Valid Delay from SCK↑
t_DSDOBUSYL SDO Data Valid Delay from BUSY↓
C_L = 20pF (Note 10)
C_L = 20pF (Note 10)
l
1
l
ns
5
ns
t_EN
Bus Enable Time After RDL↓
(Note 11)
l
16
ns
t_DIS
Bus Relinquish Time After RDL↑
(Note 11)
l
13
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OV_DD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OV_DD without
latch-up.
Note 4: V_DD = 2.5V, OV_DD = 2.5V, REF = 5V, f_SMPL = 1MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Zero-scale error is the offset voltage measured from 0.5LSB
when the output code flickers between 00 0000 0000 0000 0000 and
00 0000 0000 0000 0001. Full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale 5V input with a
5V reference voltage.
Note 9: f_SMPL = 1MHz, I_REF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OV_DD = 1.71V, OV_DD = 2.5V
and OV_DD = 5.25V.
Note 12: t_SCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OV_DD
t_DELAY
0.8*OV_DD
0.2*OV_DD
0.2*OV_DD
t_DELAY
0.8*OV_DD
0.2*OV_DD
t_WIDTH
50%
50%
Figure 1. Voltage Levels for Timing Specifications
236818 F01
236818f
5